EP0145529A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Split screen smooth scrolling arrangement
Assignee: Digital Equipment Corp
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Filing: 1984-10-17
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Granted: —
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Expires: 2004-10-17
Abstract
Abstract The present invention is employed in a system which has a bit map memory connected to a CRT display device and the CRT display device cab display a fixed region of information and a scrollable region of information. In a preffered embodiment, the system uses a graphic display control circuit (19) to change starting addresses and length ending values of the fixed and scrollable regions in the bit map memory. By changing the starting address one scan line per frame, without any actual transfer of data in memory, from one location to another location, the present system effects a «smooth» scroll. The system is able to scroll upward and downward. The system uses logic circuitry to load an off screen segment of the bit map memory with additional scrollable information, so that (in an upward scroll load) as a top line of the scrollable information region is no longer displayed, new information will be displayed at the bottom line of said scrollable region. On the other hand during a downward scroll, a bottom line of information on the scrollable region of the screen will fade out and new information is added, from the off screen region, of the bit map memory to provide information for a new top line. In addition the system has the ability to reorganize the information in the bit map memory in the event the size or location of the fixed region is to be altered.
Inventors
- 👤 Robert Salvatore Di Nitto
- 👤 Thomas Courtenay Porcher
- 👤 John Wai Eng
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 02:33
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14; G09; G09G; G09G5/00; G09G5/34; G09G5/346
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
340 words
A cathode ray tube display arrangement which is used to display information from a main computer source, and which employs a bit map memory to store pixel information to be displayed, characterized in that said display arrangement includes a circuit for effecting a split screen smooth scrolling operation comprising in combination: microprocessor means coupled to said main computer to receive instruction data and address data therefrom as well as coded text signals, said microprocessor means being formed to encode said coded text signals into arrays of bit signals defining text characters which represent said coded text; controller circuitry connected to said microprocessor means and having logic circuitry and having at least an address register and a region length register, said controller circuitry having means to store instruction signals and address signals received from said microprocessor means and further formed to increment said address register by one and to decrement said region length register by one in correspondence to each scan line of said cathode ray tube; first circuitry means connected to said microprocessor means to receive said array of bit signals therefrom and connected to said bit map memory to transmit said array of bit signals thereto; second circuitry means connected to said controller circuitry to receive address signals therefrom and connected to said bit map memory to transmit address signals thereto whereby said controller circuitry acts, in one frame, to transmit a first starting address and succeeding addresses to said bit map memory to cause pixel elements in a particular region of said bit map memory to be read, scan line after scan line, until said region length register is decremented to zero and whereby thereafter said addressing and readout procedure is repeated with each succeeding starting address differing from the preceding starting address by one scan line so that the display corresponding to the section of the bit map memory which was first addressed fades away one scan line at a time and the display appears to the viewer to move toward the portion which is fading away.
Claim 2
Dependent Claim
340 words
A cathode ray tube display arrangement which is used to display information from a main computer source, and which employs a bit map memory to store pixel information to be displayed, characterized in that said display arrangement includes a circuit for effecting a split screen smooth scrolling operation comprising in combination: microprocessor means coupled to said main computer to receive instruction data and address data therefrom as well as coded text signals, said microprocessor means being formed to encode said coded text signals into arrays of bit signals defining text characters which represent said coded text; controller circuitry connected to said microprocessor means and having logic circuitry and having at least an address register and a region length register, said controller circuitry having means to store instruction signals and address signals received from said microprocessor means and further formed to increment said address register by one and to decrement said region length register by one in correspondence to each scan line of said cathode ray tube; first circuitry means connected to said microprocessor means to receive said array of bit signals therefrom and connected to said bit map memory to transmit said array of bit signals thereto; second circuitry means connected to said controller circuitry to receive address signals therefrom and connected to said bit map memory to transmit address signals thereto whereby said controller circuitry acts, in one frame, to transmit a first starting address and succeeding addresses to said bit map memory to cause pixel elements in a particular region of said bit map memory to be read, scan line after scan line, until said region length register is decremented to zero and whereby thereafter said addressing and readout procedure is repeated with each succeeding starting address differing from the preceding starting address by one scan line so that the display corresponding to the section of the bit map memory which was first addressed fades away one scan line at a time and the display appears to the viewer to move toward the portion which is fading away.
Claim 3
Dependent Claim
76 words
A cathode ray tube display arrangement according to claim 1, characterized in that said bit map memory has a fixed region, a scrollable region and an off screen region which lies adjacent of said scrollable region, and in that said particular region is said scrollable region and in that the value in said region length register causes said addressing and readout procedure to continue and thereby to read out pixel information from said off screen region.
Claim 4
Dependent Claim
39 words
A cathode ray tube display arrangement according to claim 2, characterized in that said microprocessor means transmits new information to said off screen region and hence said pixel information read from said off screen region will be new information.
Claim 5
Dependent Claim
42 words
A cathode ray tube display arrangement according to claim 1, characterized in that said microprocessor means includes a read only memory which is formed to transmit an array of bit signals defining characters in response to receipt of said coded text signals.
Claim 6
Dependent Claim
43 words
A cathode ray tube display arrangement according to claim 1, characterized in that said controller circuitry is formed to receive graphic bit signals from said microprocessor means and formed and connected to transmit the same through a section of said first circuitry means.
Claim 7
Dependent Claim
47 words
A cathode ray tube display arrangement according to claim 5, characterized in that said first circuitry means includes a first multiplexer which is formed to pass said array of bit signals in a first mode and formed to pass said graphic bit signals in a second mode.
Claim 8
Dependent Claim
40 words
A cathode ray tube display arrangement according to claim 1, characterized in that said first circuitry means includes a buffer to receive said arrays of bit signals and hold the same until they are transmitted to said bit map memory.
Claim 9
Dependent Claim
107 words
A cathode ray tube display arrangement according to claim 1, characterized in that said bit map memory has a fixed region, a scrollable region and an off screen region, in that said particular region is said scrollable region, in that the value in said region length register causes said addressing and readout procedure to read out all of the pixel information in said off screen region, and in that thereafter the next new starting address represents the first scan line in said scrollable region so that at least a portion of said scrollable region of said bit map memory is subject to being scanned a second time.
Claim 10
Dependent Claim
53 words
A cathode ray tube display arrangement according to claim 8, characterized in that said microprocessor means transmits new information to the section of said scrollable region which was first scanned whereby when said last-mentioned section is subject to being scanned a second time new information will appear on the cathode ray tube display.
References Cited (Backward Citations)
No citation records indexed.
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