Security arrangement for microprecessor-controlled electronic equipment

Claim 2

A lock-out security arrangement for rendering electronic equipment having a normal operation inoperative after a disabling event has occurred, and for maintaining the equipment inoperative after the disabling event has terminated, comprising: (a) a microprocessor having an internal, non-volatile, protected memory accessed solely by the microprocessor and protected from interrogation external to the microprocessor, said microprocessor being operative for executing a program stored in the internal memory, said program having an operational routine for controlling the normal operation of the equipment, and a security routine for controlling the security of the equipment; (b) said security routine having means for distinguishing between an initial execution of the security routine and a subsequent execution of the security routine; (c) means responsive to the initial execution of the security routine, for storing a first code in a secured manner in the internal memory of the microprocessor such that the stored first code is protected from interrogation external to the microprocessor; (d) code entry means operatively connected to the microprocessor, for entering a second code to the microprocessor; (e) said security routine having code validity means for comparing the second code entered using the code entry means to the stored first code whose identity is protected from external interrogation; (f) enabling means responsive to a completed initial execution, or to the subsequent execution, of the security routine, for enabling the microprocessor to execute the operational routine after the first code has been stored in the internal memory of the microprocessor, and for maintaining the equipment normally operational until the disabling event has occurred; (g) detector means operatively connected to the microprocessor, for detecting when the disabling event has occurred; and (h) disabling means responsive to the detector means and operatively connected to the microprocessor, for disabling the equipment from normal operation after the disabling event has occurred, said disabling means being further operative for maintaining the equipment disabled, even after the disabling event has terminated, until the second code matches the stored first code.

Claim 3

A lock-out security arrangement for rendering electronic equipment having a normal operation inoperative after a disabling event has occurred, and for maintaining the equipment inoperative after the disabling event has terminated, comprising: (a) a microprocessor having an internal, non-volatile, protected memory accessed solely by the microprocessor and protected from interrogation external to the microprocessor, said microprocessor being operative for executing a program stored in the internal memory, said program having an operational routine for controlling the normal operation of the equipment, and a security routine for controlling the security of the equipment; (b) said security routine having means for distinguishing between an initial execution of the security routine and a subsequent execution of the security routine; (c) means responsive to the initial execution of the security routine, for storing a public code in the internal memory of the microprocessor; (d) means for substituting a private code for the public code in a secured manner in the internal memory of the microprocessor such that the stored private code is protected from interrogation external to the microprocessor; (e) code entry means operatively connected to the microprocessor, for entering a trial code to the microprocessor; (f) said security routine having code validity means for comparing the trial code entered using the code entry means to the stored private code whose identity is protected from external interrogation; (g) enabling means responsive to a completed initial execution, or to the subsequent execution, of the security routine, for enabling the microprocessor to execute the operational routine after the private code has been stored in the internal memory of the microprocessor, and for maintaining the equipment normally operational until the disabling event has occurred; (h) detector means operatively connected to the microprocessor, for detecting when the disabling event has occurred; and (i) disabling means responsive to the detector means and operatively connected to the microprocessor, for disabling the equipment from normal operation after the disabling event has occurred, said disabling means being further operative for maintaining the equipment disabled, even after the disabling event has terminated, until the trial code matches the stored private code.

Claim 4

A lock-out security arrangement for rendering electronic equipment having a normal operation inoperative after a disabling event has occurred, and for maintaining the equipment inoperative after the disabling event has terminated, comprising: (a) a microprocessor having an internal, non-volatile, protected memory accessed solely by the microprocessor and protected from interrogation external to the microprocessor, said microprocessor being operative for executing a program stored in the internal memory, said program having an operational routine for controlling the normal operation of the equipment, and a security routine for controlling the security of the equipment; (b) said security routine having means for distinguishing between an initial execution of the security routine and a subsequent execution of the security routine; (c) means responsive to the initial execution of the security routine, for storing a public code in the internal memory of the microprocessor; (d) means for substituting a private code for the public code in a secured manner in the internal memory of the microprocessor such that the stored private code is protected from interrogation external to the microprocessor; (e) code entry means operatively connected to the microprocessor, for entering a trial code to the microprocessor; (f) said security routine having code validity means for comparing the trial code entered using the code entry means to the stored private code whose identity is protected from external interrogation; (g) enabling means responsive to a completed initial execution, or to the subsequent execution, of the security routine, for enabling the microprocessor to execute the operational routine after the private code has been stored in the internal memory of the microprocessor, and for maintaining the equipment normally operational until the disabling event has occurred; (h) detector means operatively connected to the microprocessor, for detecting when the disabling event has occurred; and (i) disabling means responsive to the detector means and operatively connected to the microprocessor, for disabling the equipment from normal operation after the disabling event has occurred, said disabling means being further operative for maintaining the equipment disabled, even after the disabling event has terminated, until the trial code matches the stored private code.

Claim 5

A lock-out security arrangement for rendering electronic equipment having a normal operation inoperative after a disabling event has occurred, and for maintaining the equipment inoperative after the disabling event has terminated, comprising: (a) a microprocessor having an internal, non-volatile, protected memory accessed solely by the microprocessor and protected from interrogation external to the microprocessor, said microprocessor being operative for executing a program stored in the internal memory, said program having an operational routine for controlling the normal operation of the equipment, and a security routine for controlling the security of the equipment; (b) said security routine having means for distinguishing between an initial execution of the security routine and a subsequent execution of the security routine; (c) means responsive to the initial execution of the security routine, for storing a public code in the internal memory of the microprocessor; (d) means for substituting a first private code for the public code in a secured manner in the internal memory of the microprocessor such that the stored first private code is protected from interrogation external to the microprocessor; (e) code entry means operatively connected to the microprocessor, for entering a trial code to the microprocessor; (f) said security routine having code validity means for comparing the trial code entered using the code entry means to the stored first private code whose identity is protected from external interrogation; (g) enabling means responsive to a completed initial execution, or to the subsequent execution, of the security routine, for enabling the microprocessor to execute the operational routine after the first private code has been stored in the internal memory of the microprocessor, and for maintaining the equipment normally operational until the disabling event has occurred; (h) detector means operatively connected to the microprocessor, for detecting when the disabling event has occurred; (i) disabling means responsive to the detector means and operatively connected to the microprocessor, for disabling the equipment from normal operation after the disabling event has occurred, said disabling means being further operative for maintaining the equipment disabled, even after the disabling event has terminated, until the trial code matches the stored first private code; (j) means for changing the first private code to a second private code known only to an authorized user having knowledge of the first private code, and for storing the second private code in a secured manner in the internal memory of the microprocessor such that the stored second private code is protected from interrogation external to the microprocessor; (k) said code validity means being further operative, after the second private code has been stored, for comparing the trial code entered using the code entry means to the stored second private code whose identity is protected from external interrogation; and (1) said disabling means being still further operative for maintaining the equipment disabled, even after the disabling event has terminated, until the trial code matches the stored second private code.

Claim 6

A lock-out security arrangement for rendering electronic equipment having a normal operation inoperative after a disabling event has occurred, and for maintaining the equipment inoperative after the disabling event has terminated, comprising: (a) a microprocessor having an internal, non-volatile, protected memory accessed solely by the microprocessor and protected from interrogation external to the microprocessor, said microprocessor being operative for executing a program stored in the internal memory, said program having an operational routine for controlling the normal operation of the equipment, and a security routine for controlling the security of the equipment; (b) said security routine having means for distinguishing between an initial execution of the security routine and a subsequent execution of the security routine; (c) means responsive to the initial execution of the security routine, for storing a public code in the internal memory of the microprocessor; (d) means for substituting a first private code for the public code in a secured manner in the internal memory of the microprocessor such that the stored first private code is protected from interrogation external to the microprocessor; (e) code entry means operatively connected to the microprocessor, for entering a trial code to the microprocessor; (f) said security routine having code validity means for comparing the trial code entered using the code entry means to the stored first private code whose identity is protected from external interrogation; (g) enabling means responsive to a completed initial execution, or to the subsequent execution, of the security routine, for enabling the microprocessor to execute the operational routine after the first private code has been stored in the internal memory of the microprocessor, and for maintaining the equipment normally operational until the disabling event has occurred; (h) detector means operatively connected to the microprocessor, for detecting when the disabling event has occurred; (i) disabling means responsive to the detector means and operatively connected to the microprocessor, for disabling the equipment from normal operation after the disabling event has occurred, said disabling means being further operative for maintaining the equipment disabled, even after the disabling event has terminated, until the trial code matches the stored first private code; (j) means for changing the first private code to a second private code known only to an authorized user having knowledge of the first private code, and for storing the second private code in a secured manner in the internal memory of the microprocessor such that the stored second private code is protected from interrogation external to the microprocessor; (k) said code validity means being further operative, after the second private code has been stored, for comparing the trial code entered using the code entry means to the stored second private code whose identity is protected from external interrogation; and (1) said disabling means being still further operative for maintaining the equipment disabled, even after the disabling event has terminated, until the trial code matches the stored second private code.

Claim 7

The security arrangement as recited in claim 1, wherein the disabling even is a theft event, and the detector means is operative for detecting the removal of the equipment from its authorized location.

Claim 8

The security arrangement as recited in Claim 1, wherein the microprocessor includes an integrated circuit chip in a self-contained housing built into the equipment, said chip having a central processing unit, and said internal memory including a read-only memory in which the program is permanently stored and a read/write random access memory in which the first code is stored; and wherein the central processing unit, the read-only memory and the random access memory are all self-contained within the housing to protect the program and the stored first code from both visual and electronic examination.

Claim 9

The security arrangement as recited in claim 1, wherein a plurality of microprocessors are to be used for protecting a corresponding plurality of electronic equipment, and wherein the stored first code is different and unique for each microprocessor.

Claim 10

The security arrangement as recited in claim 6, wherein the storing means includes programming means for directing each microprocessor in response to the initial execution of the security routine to accept the different stored first code and to store the latter in the internal memory, said programming means being operative for applying a code signal to each microprocessor, each code signal being different for each microprocessor.

Claim 11

The security arrangement as recited in claim 6, wherein the storing means includes programming means for directing each microprocessor in response to the initial execution of the security routine to accept a common public code for storage and to temporarily store the common public code in the internal memory, said programming means being operative for applying an identical code signal to each microprocessor; and wherein the security routine associated with each microprocessor is operative for changing the common public code to each different first code upon entry of the latter by the respectively associated code entry means.

Claim 12

The security arrangement as recited in claim 8, wherein each code entry means is manually actuatable by each user, and wherein each different first code is selected and manually entered by each user to ensure code privacy.

Claim 13

The security arrangement as recited in claim 9, wherein the security routine of each microprocessor includes means for changing the first code selected by a user to a different private code selected by the user.

Claim 14

The security arrangement as recited in claim 6, wherein the distinguishing means associated with each microprocessor includes means for permanently loading a flag in a predetermined location in the internal memory of each microprocessor in response to the initial execution of the security routine, and wherein the storing means associated with each microprocessor is operative for directing each microprocessor when the flag is not loaded in the predetermined memory location to accept a common public code for storage and to temporarily store the common public code in the internal memory, and wherein the security routine associated with each microprocessor is operative after the flag has been loaded in the predetermined memory location to change the common public code to each different first code upon entry of the latter by respectively associated code entry means.

Claim 15

The security arrangement as recited in claim 6, wherein the security routine associated with each microprocessor includes means for programming the microprocessor with a code entry routine, and means for erasing the code entry routine in response to the initial execution of the security routine; and wherein the storing means associated with each microprocessor is operative for directing each microprocessor when the code entry routine is not erased to accept a code for storage and to store the code in the internal memory; and wherein the code validity means associated with each microprocessor is operative after the code entry routine has been erased for comparing the second code entered by the code entry means to the first code stored in the protected memory.

Claim 16

The security arrangement as recited in claim 12, wherein each storing means directs the associated microprocessor when the code entry routine is not erased to accept a common public code for storage and to temporarily store the common public code.in the internal memory, and wherein the security routine of each microprocessor is operative after the code entry routine has been erased to change the common public code to each different first code upon entry of the latter by the respectively associated code entry means.

Claim 17

The security arrangement as recited in claim 1, and further comprising user-operated means for changing the first code to a different user-selected private code by user operation of the code entry means.

Claim 18

The security arrangement as recited in claim 1, wherein the disabling event is a theft event, and the detector means is operative for detecting the removal of the equipment from its source of electrical power.

Claim 19

The security arrangement as recited in claim 15, wherein the protected memory remains non-volatile, even after removal of the electrical power source, by being connected to a battery back-up circuit.

Claim 20

The security arrangement as recited in claim 15, wherein the protected memory remains non-volatile, even after removal of the electrical power source, by constituting the protected memory as an EEPROM circuit.

Claim 21

The security arrangement as recited in claim 1, wherein the disabling means includes a time delay means for introducing a waiting period when the second code does not match the stored first code, said code validity means being inoperative until the waiting period has expired.

Claim 24

The method as recited in claim 19, and further comprising the step of providing a plurality of microprocessors for protecting a corresponding plurality of electronic equipment, and wherein the storing step is performed by storing the first code as different and unique for each microprocessor in the internal memory thereof.

Claim 25

The method as recited in claim 20, wherein the storing step is performed by directing each microprocessor in response to the initial execution of the security routine to accept the different first code and to store the latter in the internal memory, said storing step being performed by applying a code signal to each microprocessor, each code signal being different for each microprocessor.

Claim 26

The method as recited in claim 20, wherein the storing step is performed by directing each microprocessor in response to the initial execution of the security routine to accept a common public code for storage and to temporarily store the common public code in the internal memory, said storing step being performed by applying an identical code signal to each microprocessor; and further including the step of changing the common public code to each different first code upon entry of the latter during the code entering step.

Claim 27

The method as recited in claim 22, wherein the code entering step is manually performed by each user, who selects and manually enters each different first code to ensure code privacy.

Claim 28

The method as recited in claim 23, and further comprising the step of changing the first code selected by the user to a different private code selected by the user.

Claim 29

The method as recited in claim 20, wherein the distinguishing step is performed by permanently loading a flag in a predetermined location in the internal memory of each microprocessor after the initial execution of the security routine, and wherein the storing step is performed by directing each microprocessor when the flag is not loaded in the predetermined memory location to accept a common public code for storage and to temporarily store the common public code in the internal memory, and wherein the storing step is performed after the respective flag has been loaded in the predetermined memory location by changing the common public code to each different first code upon entry of the latter during the code entering step.

Claim 30

The method as recited in claim 20, wherein the distinguishing step includes the step of programming each microprocessor with a code entry routine, and the step of erasing the code entry routine after the initial execution of the security routine; and wherein the storing step is performed by directing each microprocessor when the code entry routine is not erased to accept a code for storage and to store the code in the internal memory, and wherein the comparing step is performed after the code entry routine has been erased for comparing a code entered during the code entering step to the code stored in the protected memory.

Claim 31

The method as recited in claim 26, wherein the storing step is performed when the code entry routine is not erased to accept a common public code for storage and to temporarily store the common public code in the protected memory, and wherein the storing step is performed after the code entry routine has been erased to change the common public code to each different first code upon entry of the latter during the code entering step.

Claim 32

The method as recited in claim 19, and further comprising the step of changing the first code to a different private code selected by the user entry.

Claim 33

The method as recited in claim 19, wherein the detecting step is performed by detecting the removal of the equipment from its source of electrical power.

Claim 34

The method as recited in claim 19, wherein the detecting step is performed by detecting the removal of the equipment from its authorized location.

Claim 35

The method as recited in claim 19, wherein the disabling step is performed by introducing a waiting period when the first code entered during the code entering step does not match the stored first code, said comparing step being inoperative until the waiting period has expired.