EP0145181A2
Expired / Lapsed
EP
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Halo generation for crt display symbols
Assignee: Honeywell Inc
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Filing: 1984-10-17
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Granted: —
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Expires: 2004-10-17
Abstract
Abstract Apparatus for generating halos about CRT display symbols, to distinguish them from background video, reads, from an image memory (43), video Bit signals corresponding to a CRT picture element P I.J , and the immediately surrounding CRT picture elements. A digital signal is generated therefrom representing a first Boolean function (44). The intensity of the background illumination at P I,j is unaltered, in response to a digital signal of zero, and is diminished by one-half, in response to a digital signal of ONE. A preferred embodiment reads additional signals and employs a second Boolean function.
Inventors
- 👤 Hugh Caros Hilburn
- 👤 Michael John Johnson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 23:55
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/22; G09G5/24; G09G5/28
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
326 words
Apparatus for generating a halo about symbols in video display means, characterised in that it comprises means (41) for displaying video data comprising a matrix of picture elements, denoted P X,Y ; and means for illuminating the picture elements in response to applied signals; means (40), coupled to the video display means, for generating coordinates, for providing signals representative of those coordinates, and for synchronising the illuminating means with the coordinates; means (43) for storing video bit signals, denoted B X,Y , comprising addresses corresponding to the picture elements; means (42), coupled to the storage means and to the coordinate generating means, for reading, in response to a signal from the coordinate generating means representing a generated coordinate i,j the addresses corresponding to picture elements P I-1,J-1 ; P I,J-1 ; P I+1 ,J-1; PI-1, J ; PI, J ; P I+1 , J ; P I-1 , J+l ; P I , J+1 and P I+1,J+1 ; means (44), coupled to the address reading means for generating a digital signal:- means (46), coupled to the coordinate generating means for generating, in response to a signal from the coordinate generating means representative of the generated coordinate i, j, a video background signal for producing a predetermined intensity of illumination of the picture element P I,J ; means (46), coupled to the video display means, the digital signal generating means, and the video background signal generating means, for generating, in response to a zero digital signal and the video background signal, a first signal, and for generating, in response to a ONE digital signal and the video background signal, a second signal, the picture element P I,J , being illuminated at a predetermined fraction of said predetermined intensity by the illuminating means of the video displaying means, in response to the second signal, and the picture element P I , J being illuminated by the illuminating means at said predetermined intensity, in response to the first signal.
Claim 2
Dependent Claim
326 words
Apparatus for generating a halo about symbols in video display means, characterised in that it comprises means (41) for displaying video data comprising a matrix of picture elements, denoted P X,Y ; and means for illuminating the picture elements in response to applied signals; means (40), coupled to the video display means, for generating coordinates, for providing signals representative of those coordinates, and for synchronising the illuminating means with the coordinates; means (43) for storing video bit signals, denoted B X,Y , comprising addresses corresponding to the picture elements; means (42), coupled to the storage means and to the coordinate generating means, for reading, in response to a signal from the coordinate generating means representing a generated coordinate i,j the addresses corresponding to picture elements P I-1,J-1 ; P I,J-1 ; P I+1 ,J-1; PI-1, J ; PI, J ; P I+1 , J ; P I-1 , J+l ; P I , J+1 and P I+1,J+1 ; means (44), coupled to the address reading means for generating a digital signal:- means (46), coupled to the coordinate generating means for generating, in response to a signal from the coordinate generating means representative of the generated coordinate i, j, a video background signal for producing a predetermined intensity of illumination of the picture element P I,J ; means (46), coupled to the video display means, the digital signal generating means, and the video background signal generating means, for generating, in response to a zero digital signal and the video background signal, a first signal, and for generating, in response to a ONE digital signal and the video background signal, a second signal, the picture element P I,J , being illuminated at a predetermined fraction of said predetermined intensity by the illuminating means of the video displaying means, in response to the second signal, and the picture element P I , J being illuminated by the illuminating means at said predetermined intensity, in response to the first signal.
Claim 3
Dependent Claim
16 words
Apparatus according to claim 1, characterised in that the storage means comprises an image memory (43).
Claim 4
Dependent Claim
19 words
Apparatus according to claim 1 or 2, characterised in that the video display means comprises a CRT display (41).
Claim 5
Dependent Claim
17 words
Apparatus according to any of the preceding claims, characterised in that the predetermined fraction is substantially one-half.
Claim 6
Dependent Claim
53 words
Apparatus according to any of the preceding claims, characterised in that the digital signal generating means comprises a Boolean OR gate (120) having nine input terminals; a Boolean NOT (121) gate; and a Boolean AND (122) gate coupled to receive the output signals from the Boolean OR gate and the Boolean NOT gate.
Claim 7
Dependent Claim
128 words
Apparatus according to any of the preceding claims, characterised in that the address reading means comprises a first shift register (50) comprising three compartments (51, 52, 53); a second shift register (55) comprising three compartments (56, 57, 58); a third shift register (60) comprising three compartments (61, 62, 63); a first delay (67) coupled to the first shift register (50); a second delay (70) coupled to the first delay; a third delay (71) coupled to the second delay; a fourth delay (66) coupled to the second shift register (55); a fifth delay (73) coupled to the fourth delay; a sixth delay (74) coupled to the fifth delay; a seventh delay (76) coupled to the third shift register (60); and a eighth delay (77) coupled to the seventh delay.
Claim 8
Dependent Claim
20 words
Apparatus according to claim 6, characterised in that the first, and fourth delays each comprise a shift register (67; 66).
Claim 9
Dependent Claim
24 words
Apparatus according to claim 6 or 7, characterised in that the second, third, fifth, sixth, seventh, and eighth delays each comprise a D-type flip-flop.
Claim 10
Dependent Claim
143 words
Apparatus according to any of claims 1 to 4, characterised in that each of the addresses is identified by an X and a Y binary coordinate, the video bit signals being stored only in the addresses whose X coordinate has a predetermined first binary digit, and whose Y coordinate has a predetermined first-binary-digit; in that the addresses correspond to picture elements P I-2, J-1; P I-1, J-1 ; P I, J-1 ; P I+1 , J-1 ; P I-2 , J ; P I-1,J ; p I,J ; P I+1 , J ; P I -2, J+1 ; P I -1, J +1 P I , J+l ; P I+1 , J+1 ; P I-2 , J+2 ; PI, J+2 ; P I-1 , J+2 ; P I+1 , J+2 ; and in that the digital signal generating means (44) generate a signal:-
Claim 11
Dependent Claim
197 words
Apparatus according to claim 9, characterised in that the address reading means comprises a first shift register (130) comprising four compartments (131 to 134); a first delay (170) coupled to the first shift register; a second delay (180) coupled to first delay; a third delay (181) coupled to the second delay; a fourth delay (182) coupled to the third delay; a second shift register (140) comprising four compartments (141 to 144) ; a fifth delay (171) coupled to the second shift register; a sixth delay (184) coupled to the fifth delay; a seventh delay (185) coupled to the sixth delay; an eighth delay (186) coupled to the seventh delay; a third shift register (150) comprising four compartments (151 to 154); a ninth delay (172) coupled to the third shift register; a tenth delay (190) coupled to the ninth delay; an eleventh delay (191) coupled to the tenth delay; a twelfth delay (192) coupled to the eleventh delay; a fourth shift register (160) comprising four compartments (161 to 164); a thirteenth delay (195) coupled to the fourth shift register; a fourteenth delay (196) coupled to the thirteenth delay; and a fifteenth delay (197) coupled to the fourteenth delay.
Claim 12
Dependent Claim
23 words
Apparatus according to claim 10, characterised in that the first, fifth, and said ninth delays (170, 171, 172) each comprise a shift register.
Claim 13
Dependent Claim
53 words
Apparatus according to claim 10 or 11, characterised in that the second, third, fourth, sixth, seventh, eighth,, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth delays (180 ; 181 ; 182 ; 184 ; 185 ; 186 ; 190 ; 191 ; 192 ; 195 ; 196 ; 197) each comprises a D-type flip-flop.
Claim 14
Dependent Claim
78 words
Apparatus according to any of claims 9 to 12, characterised in that the digital signal generating means comprises a first Boolean OR gate (200) having 16 input terminals; a second Boolean OR gate (201) having 4 input terminals. a Boolean NOT gate (202) coupled to receive the output signal from the second Boolean OR gate; and a Boolean AND gate (203) coupled to receive the output signals from the Boolean NOT gate and the first Boolean OR gate.
References Cited (Backward Citations)
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