Pulse code modulation translators

Claim 2

Pulse code Modulation (PCM) translator for translating a PCM input word into a PCM output word, one of said words being in accordance with a compressed code and the other with a linear code, characterized in that it is adapted to convert the binary bits of the input word into those of the output word in accordance with either the A-law or the mu-law as given by the selectable binary value of a control bit (A) which determines the digital values of several parameters (a, b, c, K'; c, d, K') of the translator.

Claim 3

PCM translator according to claim 1, characterized in that it is able to translate a compressed PCM input word including a 3-bit segment code and a 4-bit step code into a linear PCM output word by determining the function wherein J is said output word; L is said step code; a, b and c are variables; K' is related to said segment code and is dependent, together with said variables a, b and c, on said control bit (A) indicating that said input word is coded according to the A-law or mu-law.

Claim 4

PCM translator according to claim 2, characterized in that it includes : - decoder means (SDECl) for decoding said 3-bit segment code into a 1-out-of-8 code S7, S6, ..., S'1, S'Ø; - logic means (LOG1) coupled to said decoder means (SDECl) and controlled by said control bit (A) and providing the variables : the code word S7, ... Sl, SO constituting an altered segment code having a decimal value K'; - means (SIPO) for modifying said step code L by said variables a and b so as to obtain an altered step code - multiplier means coupled to said modifier means for multiplying said altered step code with 2K so as to obtain the product (L + a.2 4 + b. 2 -1 ).2 K' - and adder means (ADDl) coupled with said multiplier means and controlled by said control bit (A) to add said variable c to said product so as to obtain said output word J.

Claim 5

PCM translator according to claim 3, characterized in that said modifier means include a 6-stage first shift register (PISO) for storing the variable a, the step-code L and the variable b, and that said multiplier means include an 8-stage second shift register (SR), the output of said first shift register (PISO) being coupled to inputs of said stage of said second shift register (SR) through respective first gating means (Sl) controlled by respective bits S7, .... S1, SØ of said bits of the altered segment code which also control respective second gating means (S2) which are each associated to one of said stages and are each always in an opposite state of conductivity than the first gating means associated to this stage, all in such a manner that when said output of said first register (PISO) is coupled to that of said second register (SR) through a first gating means (S1) and a number of stages equal to said decimal value K', these stages are isolated from the other ones by a second gating means (S2).

Claim 6

PCM translator according to claim 1, characterized in that it is adapted to translate a linear PCM input word into a compressed PCM output word including a 3-bit segment code and a 4-bit step code by determining the functions wherein J is said input word; K is said segment code; L is said step code; c and d are variables K' is related to said segment code and is dependent together with c and d on said control bit (A) indicating that said output word is coded according to the A- or mu-law. 6. P C M translator according to claim 5, characterized in that it includes : - adder means (ADD2) controlled by said control bit (A) to add said variable c to said input word J to obtain an altered input word J + c and store it in a shift register (SIP02); - decoder means (SDEC2) coupled with said shift register for decoding the 8 most significant bits of said altered input word J + c into a 1-out-of-8 code S7, S6, ..., S'1, S'Ø, but by taking only the activated bit of highest power of said altered input word into account; - encoder means (ENC) coupled to said decoder means for coding said 1-out-of-8 code into said 3-bit segment code K; - logic means (LOG2) which are coupled to said decoder means (SD E C2) and controlled by said control bit (A) and which provides the variables : the code word S7, ... S1, SØ having the decimal value K'; - multiplier and adding means for multiplying said altered input word J + c by 2 -K' and adding said variable -d to this product so as to obtain said step code L.

Claim 7

PCM translator according to claim 6, characterized in that said multiplier and adder means include a 4-stage second shift register (SIP03), whose input is connected to the K' least significant stages of said first shift register (SIP02) through respective first gating means (SW7-SW0) controlled by respective ones of said code bits S7 to SØ with decimal value K', all in such a manner that the input of said first shift register (SIP02) is coupled to that of said second shift register (SIP02) through a corresponding number of stages, and means to shift the contents of four of said most significant stages of said first register into the four stages of said second register so as to obtain said step code L.

Claim 8

8 . Shift register cell with a data input coupled to a data output through the cascade connection of an input storage circuit and an output storage circuit, characterized in that it also has an auxiliary data input, said auxiliary data input and the output of said first storage circuit being coupled to the input of said second storage circuit via respective first (Sl) and second (S2) gating means having a common control input (5) and such that they are always in an opposite state of conductivity.

Claim 9

8 . Shift register cell with a data input coupled to a data output through the cascade connection of an input storage circuit and an output storage circuit, characterized in that it also has an auxiliary data input, said auxiliary data input and the output of said first storage circuit being coupled to the input of said second storage circuit via respective first (Sl) and second (S2) gating means having a common control input (5) and such that they are always in an opposite state of conductivity.

Claim 10

Shift register cell according to claim 8, characterized in that said storage circuits are each constituted by an inverter comprising the series connection between the poles of a DC source (V+, V-) of the source-to-drain paths of first (PM1) and second (PM2) PMOS transistors and of the drain-to-source paths of first (NMl) and second (NM2) NMOS transistors, the commoned gate electrodes of said first PMOS transistor (PM1) and said second NMOS transistor (NM2) constituting the inverter input ( I ) and the commoned drain electrodes of said second PMOS transistor (PM2) and said first NMOS transistor (NMl) constituting the inverter output (0).

Claim 11

10 . Shift register cell according to claim 8, characterized in that each of said gating means (Sl, S2) comprises a PMOS transistor whose drain and source electrodes are connected to the source and drain electrodes of an NMOS transistor respectively and constitute the data input and output of the gating means and whose gate electrodes constitute the control inputs of the gating means.

Claim 12

Multiplier device for multiplying a binary word stored in a first shift register with 2 x , with x = Ø, ..., K by shifting said word through x stages of a second shift register, characterized in that said' Second shift register (SR) includes K(8) stages, that the output of said first shift register (PISO) is coupled with the K stages of said second shift register via K respective first gating means (Sl) which are controlled by respective bits (SØ, ..., S7) of a binary 1-out-of K code which has said decimal value x, and that to each of said stages is associated a second gating means ( S2), the second gating means being controlled by said respective bits (SØ, ..., S7) all in such a way that when a first gating means (Sl) establishes a connection between the output of the first shift register ( PIS O) and a stage of the second shift register (SR), the latter stage is isolated from the other stages of this shift register by the second gating means (S2) associated therewith.

Claim 13

Multiplier device for multiplying a binary word stored in a first shift register with 2 x , with x = Ø, ..., K by shifting said word through x stages of a second shift register, characterized in that said' Second shift register (SR) includes K(8) stages, that the output of said first shift register (PISO) is coupled with the K stages of said second shift register via K respective first gating means (Sl) which are controlled by respective bits (SØ, ..., S7) of a binary 1-out-of K code which has said decimal value x, and that to each of said stages is associated a second gating means ( S2), the second gating means being controlled by said respective bits (SØ, ..., S7) all in such a way that when a first gating means (Sl) establishes a connection between the output of the first shift register ( PIS O) and a stage of the second shift register (SR), the latter stage is isolated from the other stages of this shift register by the second gating means (S2) associated therewith.

Claim 14

Device according to claim 4 or 11 , characterized in that each of said stages of said second shift register (S R ) and the first and second gating means associated to said stage constitute a shift register all as per any of the claims 8 to 10.

Claim 15

Device according to claim 4 or 11, characterized in that each of said stages of said first shift register (PISO) and is constituted by a shift register cell as per any of the claims 8 to 10 but only with first gating means (S1).