EP0144249A2
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EP
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Buffer storage system
Assignee: Fujitsu Ltd
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Filing: 1984-12-07
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Granted: —
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Expires: 2004-12-07
Abstract
Abstract A buffer storage system for a pipeline processor, set up with at least an operand access buffer storage (2), an instruction fetch buffer storage (5), an operand effective address register (1), an instruction effective address register (4), an operand store data register (7), and an instruction store data register (8). The operand registers (1, 7) and instruction registers (4, 8) cooperate with store address registers (9) and store data registers (10), to assume a store-through method between the buffer storages (2, 5) and a main storage. A feedback means (L A , Lp) is mounted between the instruction registers (4, 8) and the store address/data registers (9, 10). This feedback means is activated during an operand store operation to apply an operand store address and an operand store data, from the store address registers (9) and store data registers (10), to the instruction effective address register (4) and the instruction store data register (8) respectively, for effecting coincidence in data among the storages (2, 5).
Inventors
- 👤 Tone Hirosada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 23:04
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3812; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848; G06F9/3824; G06F9/3867
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
175 words
A buffer storage system operatively connected with an instruction unit, an execution unit, and a main storage to set up a pipeline processor, comprising: an operand access buffer storage accessed by an operand store address or an operand fetch address given from said instruction unit, the accessed being operand data therefrom A transferred to said execution unit; an instruction fetch buffer storage accessed by an instruction fetch address given from said instruction unit, the accessed instruction data being returned to said instruction unit; and information registers comprising store address registers and store data registers, activated during an operand store operation, which register(in the buffer) said operand store address and operand store data, respectively, sent from said execution unit and then transfer the buffered data to said main storage to assume a store-through method, characterized in that the buffer storage system includes therein a feedback means for applying the buffered operand store address and operand store data,(both) buffered in asaid store address register and a said store data register, respectively, to said instruction fetch buffer storage.
Claim 2
Dependent Claim
175 words
A buffer storage system operatively connected with an instruction unit, an execution unit, and a main storage to set up a pipeline processor, comprising: an operand access buffer storage accessed by an operand store address or an operand fetch address given from said instruction unit, the accessed being operand data therefrom A transferred to said execution unit; an instruction fetch buffer storage accessed by an instruction fetch address given from said instruction unit, the accessed instruction data being returned to said instruction unit; and information registers comprising store address registers and store data registers, activated during an operand store operation, which register(in the buffer) said operand store address and operand store data, respectively, sent from said execution unit and then transfer the buffered data to said main storage to assume a store-through method, characterized in that the buffer storage system includes therein a feedback means for applying the buffered operand store address and operand store data,(both) buffered in asaid store address register and a said store data register, respectively, to said instruction fetch buffer storage.
Claim 3
Dependent Claim
42 words
A system as set forth in claim 1, wherein said feedback means is realized with an address bus line and a data bus line, both connected between said instruction fetch buffer storage and both said store address registers and store data registers,respectively.
Claim 4
Dependent Claim
103 words
A system as set forth in claim 2, wherein said operand access buffer storage is provided with an operand store data register for momentarily holding block data given from said main storage or said operand store data; said instruction fetch buffer storage is provided with an instruction effective address register and an instruction store data register; the instruction holding effective address register momentarily holding said operand store address transferred via said address bus line and said instruction fetch address selectively; and said instruction store data register momentarily holding said operand store data transferred via said data bus line and said block data, selectively.
Claim 5
Dependent Claim
122 words
A system as set forth in claim 3, wherein a retry means is further incorporated in the buffer storage system, the retry means being operative to produce a retry signal for commanding a retry of an related to an operand access operation, in a case instruction fetch operation related to an operand access operation, in a case when an instruction fetch address is set in said instruction effective address a register after an operand store address is set in a said store address register but before said applying to the instruction fetch buffer storage by said feedback means is completed and the instruction fetch address is the same as the operand store address set in any one of said store address registers.
Claim 6
Dependent Claim
70 words
A system as set forth in claim 4, wherein said retry means is comprised of a logic gate having a plurality of inputs and an output for producing said being retry signal, the inputs connected with the outputs of comparators, respectively; the comparators receiving at first comparing inputs, the outputs from said store address registers, respectively, and eceiving at their second comparing inputs, outputs from said instruction effective address register.
Claim 7
Dependent Claim
46 words
A system as set forth in claim 5, wherein one of said inputs of said logic gate receives a signal indicating that all said store address registers are full of respective operand store addresses, thereby producing from the output of the logic gate said retry signal.
Claim 8
Dependent Claim
41 words
A system as set forth in claim 6, wherein the buffer storage system has further incorporated therein a save register, as a said information register, storing the for said related instruction fetch operation instruction fetch address for performing said retry operation.
Claim 9
Dependent Claim
20 words
A system as set forth in claim 6, wherein the buffer storage system is controlled by means of control registers.
Claim 10
Dependent Claim
173 words
A system as set forth in claim 8, wherein VR flag registers and BM registers are employed as said control registers; both each said store address register and corresponding said store data register compose a store buffer register, and thus, a plurality of store buffer registers are constructed fcr each pair of said store address and store data registers; each of the store buffer registers is provided with the VR register and the BM register; each of the VR flag registers sets therein a V flag, i.e., valid flag, and an R flag, i.e., ready flag, and each of the BM register sets therein a BM, i.e., a byte mark; each said V flag indicates that the operand store address has been stored in the corresponding one of said store address registers, each said R flag indicates that the operand store data has been stored in the corresponding one of said store data registers, and each said byte marks indicates a byte location of the operand store data in said store data register.
Claim 11
Dependent Claim
108 words
A system as set forth in claim 9, wherein the buffer storage system further incorporates therein H flag registers and I flag registers as said control wherein registers; wherein each of the H flag registers stores therein an H flag, i.e., a hold flag, indicating that the operand store data to be fed back to said instruction fetch buffer storage is being held in one of said store and data registers; and each of the I flag registers stores therein an . I flag, i.e., an issue flag, indicating that an operand store access to the instruction fetch buffer storage has been issued to an instruction fetch pipeline.
Claim 12
Dependent Claim
50 words
A system as set forth in claim 10, wherein identification bit registers are further incorporated in the buffer storage system, as said control registers, the identification bit indicating . from which one of the store data registers the operand store data is to be brought into said instruction fetch pipeline.
Claim 13
Dependent Claim
49 words
A system as set forth in claim 11, wherein said information registers and control registers are cyclically selected one by one, cyclic selections being achieved by pointers synchronized with the advance of said identification bit, each of the pointers containing therein an incrementer to produce cyclic pointing addresses sequentially.
References Cited (Backward Citations)
No citation records indexed.
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