Patent US1560520A successfully refreshed from Google Patents.
EP0143652A2
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Process for forming multi-layer interconnections
Assignee: Toshiba Corp
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Filing: 1984-11-28
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Granted: —
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Expires: 2004-11-28
Abstract
Abstract @ First conductive members (6b) are buried in first holes (5b) formed in a first insulating film (3) to connect a second interconnection layer (12), formed through first and second insulating films (3), (8) to a semiconductor substrate (1). Second conductive members (11) are buried in second holes (10), formed to be positioned on the first holes (5b) of the second insulating film (8). Thus, the reliability of a semiconductor device of multi-layer interconnection structure is improved, and the integration thereof is improved.
Inventors
- 👤 Yoshikazu C/O Patent Division Hazuki
- 👤 Takahiko C/O Patent Division Moriya
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 10:37
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/057
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
132 words
A process for forming multi-layer interconnections including at least first and second interconnection layers in a semiconductor device comprising the steps of: forming a first insulating film on a semiconductor substrate, the semiconductor substrate having circuit elements; forming first holes in the first insulating film; burying first conductive members in the first holes; forming first interconnection layers on the first insulating film; forming a second insulating film on the first insulating film, on which the first interconnection layers are formed; forming second holes in the second insulating film to be positioned at least in part over the first holes; burying second conductive members in the second holes; and forming the second interconnection layers contacting the second conductive members on the second insulating film to connect the second interconnection layers to the substrate.
Claim 2
Dependent Claim
132 words
A process for forming multi-layer interconnections including at least first and second interconnection layers in a semiconductor device comprising the steps of: forming a first insulating film on a semiconductor substrate, the semiconductor substrate having circuit elements; forming first holes in the first insulating film; burying first conductive members in the first holes; forming first interconnection layers on the first insulating film; forming a second insulating film on the first insulating film, on which the first interconnection layers are formed; forming second holes in the second insulating film to be positioned at least in part over the first holes; burying second conductive members in the second holes; and forming the second interconnection layers contacting the second conductive members on the second insulating film to connect the second interconnection layers to the substrate.
Claim 3
Dependent Claim
35 words
The process according to claim 1, characterized in that said first and second conductive members are refractory metals deposited by a selective chemical vapor deposition using a refractory metal halide gas and a hydrogen gas.
Claim 4
Dependent Claim
40 words
The process according to claim 1, characterized in that said first and second conductive members are refractory metal silicides deposited by a selective chemical vapor deposition using a refractory metal halide gas; a gas including silicon and a hydrogen gas.
Claim 5
Dependent Claim
36 words
The process according to claim 1, characterized in that auxiliary conductive layers are formed on the first conductive members to be positioned beneath the second conductive members at the steps of forming the first interconnection layers.
Claim 6
Dependent Claim
54 words
The process according to claim 1, characterized in that third holes are formed in the first insulating film at the step of forming the first holes, and third conductive members are buried in the third holes to connect the first interconnection layers to the substrate at the step of burying the first conductive members.
References Cited (Backward Citations)
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