EP0143596A2
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EP
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Programmable read-only memory device
Assignee: Fujitsu Ltd
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Filing: 1984-11-20
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Granted: —
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Expires: 2004-11-20
Abstract
Abstract A programmable read-only memory device comprises a memory cell transistor (Q 3 ) which has a source, a drain, a floating gate, and a control gate formed over the floating gate. Programming of the device is performed by applying a high voltage (RWS) to the control gate and a high voltage (CLM) to the drain of the memory cell transistor. The high voltages are applied to the memory cell transistor under the control of respective program signals (DPGM, PGM). The device further comprises means (Q 4 -Q 11 , C l -C 3 ) for delaying the program signal (DPGM) for the control gate voltage, relative to the program signal (PGM) for the drain voltage, during the programming operation. The application of the programming voltage to the control gate is therefore delayed relative to the application of the programming voltage to the drain, which ensures reliable data writing even if the programming voltage level is less than normal.
Inventors
- 👤 Manabu Tsuchida
- 👤 Masanobu Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 16:16
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/32; G11C17/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
111 words
A programmable read-only memory device comprising a memory cell transistor (Q 3 ) having a source (1), a drain (2), a floating gate (4), and a control gate (6) formed above the floating gate; and characterised by delay means (Q 4 -Q 11 ' C 1 C 3 ) for delaying the timing of the application of a high programming voltage (RWS) to the control gate relative to that of the application of a high programming voltage (CLM) to the drain of the memory cell transistor when a data programming operation is performed by applying the high programming voltages to the control gate and the drain of the memory cell transistor.
Claim 2
Dependent Claim
111 words
A programmable read-only memory device comprising a memory cell transistor (Q 3 ) having a source (1), a drain (2), a floating gate (4), and a control gate (6) formed above the floating gate; and characterised by delay means (Q 4 -Q 11 ' C 1 C 3 ) for delaying the timing of the application of a high programming voltage (RWS) to the control gate relative to that of the application of a high programming voltage (CLM) to the drain of the memory cell transistor when a data programming operation is performed by applying the high programming voltages to the control gate and the drain of the memory cell transistor.
Claim 3
Dependent Claim
94 words
A memory device according to claim 1, characterised by means (G 2 ,Q 15 -Q 17 ) for generating a column selection signal (CLM) which applies the high programming voltage to the drain of the memory cell transistor of a selected column under the control of a program signal (PGM); and means (G 1 ,Q 12 -Q 14 ) for generating a row selection signal (RWS) which applies the high programming voltage to the control gate of the memory cell transistor of a selected row under the control of a delayed program signal (DPGM).
Claim 4
Dependent Claim
34 words
A memory device according to claim 2, characterised in that the delay means (Q 4 -Q 11' C 1 -C 3 ) delays the program signal (PGM) to generate the delayed program signal (DPGM).
Claim 5
Dependent Claim
141 words
A memory device according to claim 2 or claim 3, characterised in that the means for generating a row selection signal (RWS) comprises a gate circuit (G 1 ) for decoding input row addresses (ADD); a first high withstand voltage depletion type transistor (Q 12 ) the source of which is connected to the output of the gate circuit and the gate of which receives a power supply voltage (V CC ); and a series connection of a second high withstand voltage non-dose type transistor (Q 13 ) the gate of which receives the delayed program signal (DPGM) and a third high withstand voltage deep depletion type transistor (Q 14 ) the gate and source of which are interconnected, the series connection being inserted between a high voltage power supply voltage (V PP ) and the drain of the first transistor.
Claim 6
Dependent Claim
139 words
A memory device according to claim 2 or claim 3, characterised in that the means for generating a column selection signal (CLM) comprises a gate circuit (G 2 ) for decoding input column addresses (ADD); a first high withstand voltage depletion type transistor (Q 15 ) the source of which is connected to the output terminal of the gate circuit and the gate of which receives a power supply voltage (V CC ); and a series connection of a second high withstand voltage non-dose type transistor (Q 16 ) the gate of which receives the program signal (PGM) and a third high withstand voltage deep depletion type transistor (Q 17 ) the gate and source of which are interconnected, the series connection being inserted between a high voltage power supply voltage (Vpp) and the drain of the first transistor.
Claim 7
Dependent Claim
61 words
A memory device according to any preceding claim, characterised in that the delay means comprises one or more inverters (Q 4 ,Q 5 ;Q 6 ,Q7;Q 8 ,Q 9 ;Q 10 ,Q 11 ) connected in cascade, and one or more capacitors (C 1 ,C 2 ,C 3 ) each connected to the output of a respective one of the inverters.
Claim 8
Dependent Claim
160 words
A memory device according to claim 1, characterised in that the memory device further comprises means (G 4 ,Q 50 -Q 53 ) for generating a column selection signal (CLM) which applies a high programming voltage to the drain of the memory cell transistor of a selected column; a first power switch circuit (Q 24 -Q 34 ) for generating an internal power supply voltage (V PPI (C)) which is fed to the column selection signal generating means under the control of a program signal (PGMC); means (G 3 ,Q 46 -Q 49 ) for generating a row selection signal (RWS) which applies a high programming voltage to the control gate of the memory cell transistor of a selected row; and a second power switch circuit (Q 35 -Q 45 ) for generating an internal power supply voltage (V PPI (R)) which is fed to the row selection signal generating means under the control of a delayed program signal (PGMR).
Claim 9
Dependent Claim
26 words
A memory device according to claim 7, characterised in that the delay means (Q18-Q23) delays the program signal (PGMC) to generate the delayed program signal (PGMR).
Claim 10
Dependent Claim
64 words
A memory device according to claim 8, characterised in that the delay means comprises an integration circuit having a parallel connection of an N-channel MIS taransistor (Q 20 ) and a P-channel MIS transistor (Q 21 ) inserted between an input and an output of the integration circuit, and capacitor means (C 4 ,C 5 ) connected between the output and a power source.
Claim 11
Dependent Claim
102 words
A memory device according to any one of claims 7 to 9, characterised in that the first power switch circuit comprises first and second high withstand voltage transistors (Q31,Q32) which are alternatively turned on by the program signal (PGMC), the first high withstand voltage transistor (Q 31 ) supplying a high internal power supply voltage (V PPI (C)) to the column selection signal generating means when it is turned on, and the second high withstand voltage transistor (Q 32 ) supplying a low internal power supply voltage (V CC ) to the column selection signal generating means when it is turned on.
Claim 12
Dependent Claim
107 words
A memory device according to any one of claims 7 to 9, characterised in that the second power switch circuit comprises first and second high withstand voltage transistors (Q 42 ,Q 43 ) which are alternatively turned on by the delayed program signal (PGMR), the first high withstand voltage transistor (0 42 ) supplying a high internal power supply voltage (V PPI (R)) to the row selection signal generating means when it is turned on, and the second high withstand voltage transistor (Q 43 ) supplying a low internal power supply voltage (V CC ) to the row selection signal generating means when it is turned on.
Claim 13
Dependent Claim
180 words
A memory device according to any one of claims 7 to 11, characterised in that the means for generating a row selection signal (RWS) comprises a gate circuit (G 3 ) for decoding input row addresses (ADD), a first high withstand voltage type transistor (° 46 ) the soruce of which is connected to the output of the gate circuit and the gate of which receives a power supply voltage (V CC ); a CMIS inverter comprising high withstand voltage MIS transistors (Q 48 ,Q 49 ) the input of which is connected to the drain of the first transistor (Q 46 ) and which is operated by the internal power supply voltage (V PPI (R)) supplied from the second power switch circuit (Q 35 -Q 45 ); and a second high withstand voltage type transistor which is connected between the second power transistor (Q 47 ) which is connected between the second power switch circuit and the drain of the first transistor (0 46 ) and the gate of which receives the output signal (RWS) of the CMIS inverter.
Claim 14
Dependent Claim
172 words
A memory device according to any one of claims 7 to 12, characterised in that the means for generating a column selection signal (CLM) comprises a gate circuit (G 4 ) for decoding input column addresses (ADD); a first high withstand voltage type transistor (Q 50 ) the source of which is connected to the output of the gate circuit and the gate of which receives a power supply voltage (V CC ); a CMIS inverter comprising high withstand voltage MIS transistors (Q 52 ,Q 53 ) the input of which is connected to the drain of the first transistor (Q 50 ) and which is operated by the internal power supply voltage (V PPI (C)) supplied from the first power switch circuit (Q 24 -Q 34 ); and a second high withstand voltage type transistor (Q 51 ) which is connected between the first power switch circuit and the drain of the first transistor (Q 52 ) and the gate of which receives the output signal (CLM) of the CMIS inverter.
References Cited (Backward Citations)
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