Parallel adder circuit

Claim 2

A full adder circuit comprising: an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal, and a carry output terminal; a control circuit (21) responsive to an addend input signal (Ai) and an augend input signal (Bi) applied to said addend input terminal and augend input terminal respectively, for providing a-switch control signal (φ, φ ) which goes to a first logic level when the addend input signal and augend input signal are equal and which goes to a second logic level when they are not equal; an input circuit (22) responsive to the addend and augend input signals for providing a NAND output signal or NOR output signal of the addend and augend input signals or an inverted signal of one of the addend and augend input signals; and a switching circuit having first to fourth inverting type switching means (S 5 to S 8 ) responsive to the switch control signal (φ, φ ) said first and fourth switching means (S 5 , Sg) being enabled to invert an input signal applied thereto when the switch control signal from said control circuit is at the first logical level, said second and third switching means (S 6 , S 7 ) being enabled to invert an input signal thereto when the switch control signal from said control circuit is at the second logical level, said first and second switching means (S 5 , S 6 ) being connected to respectively receive a carry inverted input signal (C i-1 ) applied to said carry input terminal and its inverted signal, and having their outputs connected together to said sum output terminal, and said third and fourth switching means (S 7 , Sg) being connected to respectively receive the carry inverted input signal (C i-1 ) applied to said carry input terminal and an output signal of said input circuit (22), and having their outputs connected together to said carry output terminal.

Claim 3

A full adder circuit comprising: an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal and a carry output terminal; a control circuit (24) responsive to an addend input signal (Ai) and an augend input signal (B i ) applied to said addend and augend input terminals for providing a switch control signal (6, φ ) which goes to a first logic level when the addend input signal and augend input signal are equal and which goes to a second logic level when the input signals are not equal; an input circuit (25) responsive to the addend and augend input signals for providing one of the input signals as an output signal; and a switching circuit having first to fourth inverting type switching means (S 9 to S 12 ) responsive to the switch control signal, said second and fourth switching means (S 10' S 12 ) being enabled to invert an input signal applied thereto when the switch control signal is at the first logic level, said first and third switching means (S 9' S ll ) being enabled to inverted an input signal applied thereto when the switch control signal is at the second logic level, said first and second switching means (S 9' S 10 ) being connected to respectively receive a carry input signal (C i-1 ) applied to said carry input terminal and its inverted signal, and having their outputs connected together to said sum output terminal, and said third and fourth switching means (S 11 , S 12 ) being connected to respectively receive the carry input signal applied to said carry input terminal and an output signal of said input circuit, and having their outputs connected together to said carry output terminal.

Claim 4

A full adder circuit comprising: an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal and a carry output terminal; a control circuit (24) responsive to an addend input signal (Ai) and an augend input signal (B i ) applied to said addend and augend input terminals for providing a switch control signal (6, φ ) which goes to a first logic level when the addend input signal and augend input signal are equal and which goes to a second logic level when the input signals are not equal; an input circuit (25) responsive to the addend and augend input signals for providing one of the input signals as an output signal; and a switching circuit having first to fourth inverting type switching means (S 9 to S 12 ) responsive to the switch control signal, said second and fourth switching means (S 10' S 12 ) being enabled to invert an input signal applied thereto when the switch control signal is at the first logic level, said first and third switching means (S 9' S ll ) being enabled to inverted an input signal applied thereto when the switch control signal is at the second logic level, said first and second switching means (S 9' S 10 ) being connected to respectively receive a carry input signal (C i-1 ) applied to said carry input terminal and its inverted signal, and having their outputs connected together to said sum output terminal, and said third and fourth switching means (S 11 , S 12 ) being connected to respectively receive the carry input signal applied to said carry input terminal and an output signal of said input circuit, and having their outputs connected together to said carry output terminal.

Claim 5

A parallel adder circuit comprising: first and second full adders (Xi to X n/2 , Y l to Y n/2 ) each having an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal, and a carry output terminal, said first and second full adders being alternately connected such that the carry output terminal of a preceding full adder is directly connected to the carry input terminal of a succeeding full adder; each of said first full adders (X 1 to Xn /2 ) including; a first control circuit (21) responsive to an addend input signal (Ai) and an augend input signal (Bi) applied to said addend input terminal and augend input terminal for providing a first switch control signal (φ, φ ) which goes to a first logic level when the addend input signal and augend input signal are equal and which goes to a second logic level when they are not equal; a first input circuit (22) responsive to the addend and augend input signals for providing a NAND output signal or NOR output signal of the addend and augend input signals or an inverted signal of one of the addend and augend input signals and a first switching circuit having first to fourth inverting type switching means (S 5 to Sg) responsive to the first switch control signal, said first and fourth switching means (S 5 , S 8 ) being enabled to invert an input signal applied thereto when the first switch control signal is at the first logic level, said second and third switching means (S 6 , S 7 ) being enabled to invert an input signal applied thereto when the first switch control signal is at the second logic level, said first and second switching means (S 5 , S 6 ) being connected to respectively receive a carry inverted input signal (C i-1 ) applied to said carry input terminal and its inverted signal, and having their outputs connected together to said sum output terminal, and said third and fourth switching means (S 7 , S 8 ) being connected to respectively receive the carry inverted input signal applied to said carry input terminal and an output signal of said first input circuit, and having their outputs connected together to said carry output terminal; and each of said second full adders (Y 1 to Y n/2 ) comprising: a second control circuit (24) responsive to the addend and augend input signals (Ai, Bi) for providing a second switch control signal (6, which goes the first logic level when the addend input signal and augend input signal are equal and which goes to the second logic level when the input signals are not equal; a second input circuit (25) responsive to-the addend and augend input signals for providing one of the input signals as an output signal; and a second switching circuit having fifth to eighth inverting type switching means (S 9 to S 12 ) responsive to the second control signal, said sixth and eighth switching means (S 10 , S 12 ) being enabled to invert an input signal applied thereto when the second switch control signal is at the first logic level, said fifth and seventh switching means (S 9 , S ll ) being enabled to invert an input signal applied thereto when the second switch control signal is at the second logic level, said fifth and sixth switching means (Sg, S 10 ) being connected to respectively receive a carry input signal (Ci-i) applied to said carry input terminal and its inverted signal, and having their outputs connected together to said sum output terminal, and said seventh and eighth switching means (S 11 . S 12 ) being connected to respectively receive the carry input signal applied to said carry input terminal and an output signal of said second input circuit, and having their outputs connected together to said carry output terminal.

Claim 6

A parallel adder circuit comprising: first and second full adders (Xi to X n/2 , Y l to Y n/2 ) each having an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal, and a carry output terminal, said first and second full adders being alternately connected such that the carry output terminal of a preceding full adder is directly connected to the carry input terminal of a succeeding full adder; each of said first full adders (X 1 to Xn /2 ) including; a first control circuit (21) responsive to an addend input signal (Ai) and an augend input signal (Bi) applied to said addend input terminal and augend input terminal for providing a first switch control signal (φ, φ ) which goes to a first logic level when the addend input signal and augend input signal are equal and which goes to a second logic level when they are not equal; a first input circuit (22) responsive to the addend and augend input signals for providing a NAND output signal or NOR output signal of the addend and augend input signals or an inverted signal of one of the addend and augend input signals and a first switching circuit having first to fourth inverting type switching means (S 5 to Sg) responsive to the first switch control signal, said first and fourth switching means (S 5 , S 8 ) being enabled to invert an input signal applied thereto when the first switch control signal is at the first logic level, said second and third switching means (S 6 , S 7 ) being enabled to invert an input signal applied thereto when the first switch control signal is at the second logic level, said first and second switching means (S 5 , S 6 ) being connected to respectively receive a carry inverted input signal (C i-1 ) applied to said carry input terminal and its inverted signal, and having their outputs connected together to said sum output terminal, and said third and fourth switching means (S 7 , S 8 ) being connected to respectively receive the carry inverted input signal applied to said carry input terminal and an output signal of said first input circuit, and having their outputs connected together to said carry output terminal; and each of said second full adders (Y 1 to Y n/2 ) comprising: a second control circuit (24) responsive to the addend and augend input signals (Ai, Bi) for providing a second switch control signal (6, which goes the first logic level when the addend input signal and augend input signal are equal and which goes to the second logic level when the input signals are not equal; a second input circuit (25) responsive to-the addend and augend input signals for providing one of the input signals as an output signal; and a second switching circuit having fifth to eighth inverting type switching means (S 9 to S 12 ) responsive to the second control signal, said sixth and eighth switching means (S 10 , S 12 ) being enabled to invert an input signal applied thereto when the second switch control signal is at the first logic level, said fifth and seventh switching means (S 9 , S ll ) being enabled to invert an input signal applied thereto when the second switch control signal is at the second logic level, said fifth and sixth switching means (Sg, S 10 ) being connected to respectively receive a carry input signal (Ci-i) applied to said carry input terminal and its inverted signal, and having their outputs connected together to said sum output terminal, and said seventh and eighth switching means (S 11 . S 12 ) being connected to respectively receive the carry input signal applied to said carry input terminal and an output signal of said second input circuit, and having their outputs connected together to said carry output terminal.

Claim 7

An adder circuit according to claim 1, 2 or 3, characterized in that said inverting type switching means are clocked inverters.

Claim 8

An adder circuit according to claim 1, 2 or 3, characterized in that each of the first and second switch control signals has complementary control signals.