Redundancy circuit for a semiconductor memory device

Abstract

Abstract A redundancy circuit for a semiconductor memory device of the byte configuration type, in which data is read out for each bit, is comprised of a main memory having a plurality of main memory cells arrayed in a matrix fashion, the matrix array being divided into memory sections (31, 32) in the column direction; a spare memory for saving defective memory cells contained in the main memory, the spare memory comprising spare rows (41-45) of a plurality of spare memory cells arranged in the row direction, the spare row being provided for each of the main memory sections; programmable spare row decoders (45-48) provided foreach row of spare memory cells and for independently selecting each row of the spare memory cell; and main-decoder-disable signal-generating circuits (49, 50) provided for each ofthe memory sections and for placing all of the row main decoders of the corresponding memory section in non-select state in response to a signal derived from the programmed spare row decoder of the corresponding memory section.

Inventors

• 👤 Makoto C/O Patent Division Segawa
• 👤 Shoji C/O Patent Division Ariizumi

Bibliographic Details