Millimeter wave high-power limiter using p-i-n diodes, and method of making these diodes

Claim 2

A high power limiter comprising a rectangular wave guide (2) with a longitudinal axis (A), with dimensions permitting the propagation of millimetric waves, and a silicon integrated circuit (3) having a parallelepipedon form, with a perpendicular rectangular section substantially of the same dimensions as those of the perpendicular section of the guide, mounted in the guide transversally in relation to the longitudinal axis of the same, and constituting a series-parallel matrix of PIN diodes (5) with the same dimensions, such diodes being made in a plurality of parallel silicon regions, separated from each other by furrows and electrically connected by a metallisation (8) which covers the flanks of the silicon regions and the flood of the furrows, the P + , I and N + of the diodes being placed facing the entrance of the power into the guide, characterized in that the said plurality of silicon regions forms separate rods (11), such rods being each of the same length as the perpendicular section of the circuit and being integrated by the metallisation (8) and in that the dimension (L3') of the silicon along the longitudinal axis (Δ) of the wave guide is equal to the that of the I zone of each of the diodes along the same axis (A).

Claim 3

The limiter as claimed in claim 1 characterized in that the dimensions (L' 3 ) of the silicon rods (11) along the longitudinal axis (Δ) of the wave guide is of the order to 25 microns.

Claim 4

The limiter as claimed in claim 1 or claim 2 characterized in that the two opposite longitudinal flanks (11a and 11 b) of each rod present in relation to each other the form of opposite identical crenelations thus forming silicon parts which are alternatively protruding and withdrawn, the withdrawn parts of the rods constituting the I zones of the PIN diodes (5), the protruding parts (12) of the rods constituting the capacity reduction zones between PIN diodes (5).

Claim 5

The limiter as claimed in claim 3 characterized in that the P + and N + zones of the PIN diodes (5) are alternatingly placed, each being on the two opposite flanks of a given furrow (13) separating two silicon rods, the P+ and N + zones each having a dimension along the longitudinal axis (Δ) of the guide equal to that of the I zone of the PIN diodes (5) along this same axis.

Claim 6

The limiter as claimed in claim 4 characterized in that the metallisation (8) comprises metallic layers constituting the contacts on the alternating P + and N zones of the PIN diodes, in that the metallic layers of the P + zones are linked with a first metallic common connection (9) and in that the metallic layers of the N + zones are all connected with a second metallic common connection (14).

Claim 7

A process for the manufacture of silicon PIN diodes in accordance with a series parallel configurations for a high power limiter comprising a rectangular wave guide with a longitudinal axis and with dimensions permitting the propagation of millimetric waves, comprising, starting with a silicon substrate (3), the following steps:

Claim 8

A process for the manufacture of silicon PIN diodes in accordance with a series parallel configurations for a high power limiter comprising a rectangular wave guide with a longitudinal axis and with dimensions permitting the propagation of millimetric waves, comprising, starting with a silicon substrate (3), the following steps:

Claim 9

a) the deposit of a silicon dioxide barrier layer (17) and then of a thick layer of polycrystalline silicon (18) on one of the two opposite parallel faces of the substrate, thus forming a support for the substrate; b) reduction of the substrate (3) to a given thickness (L' 3 ); c) action on the silicon substrate (3) over all its thickness in order to form furrows (13) thus delimiting longitudinal identical silicon rods (11), each furrow (13) having two opposite flanks presenting longitudinally in relation to each other a configuration of identical opposite crenelations so that each rod (11) longitudinally presents alternately withdrawn and protruding parts of the rods constituting the 1 zones of the diodes; d) a first diffusion of doped silicon of the P + type implemented at one of two furrows and on each of the opposite flanks of the same furrow, thus forming the P + zones of the diodes; e) a second diffusion of doped silicon of the N + type realized for each furrow remaining once in the preceding step effected and on each of the two opposite flanks of the same remaining furrow, thus forming the N + zones of the diodes; f) a metallic covering of all the furrows (3) of the complex structure of the preceding step; g) a withdrawal of the layer of polycrystalline silicon forming a support (18); and h) severing the assembly formed by several rods of silicon (11) effected at the level of the metallic coverings delimiting this assembly of rods, this permitting the production of a matrix of PIN diodes (5) in a series-parallel configuration.

Claim 10

a) the deposit of a silicon dioxide barrier layer (17) and then of a thick layer of polycrystalline silicon (18) on one of the two opposite parallel faces of the substrate, thus forming a support for the substrate; b) reduction of the substrate (3) to a given thickness (L' 3 ); c) action on the silicon substrate (3) over all its thickness in order to form furrows (13) thus delimiting longitudinal identical silicon rods (11), each furrow (13) having two opposite flanks presenting longitudinally in relation to each other a configuration of identical opposite crenelations so that each rod (11) longitudinally presents alternately withdrawn and protruding parts of the rods constituting the 1 zones of the diodes; d) a first diffusion of doped silicon of the P + type implemented at one of two furrows and on each of the opposite flanks of the same furrow, thus forming the P + zones of the diodes; e) a second diffusion of doped silicon of the N + type realized for each furrow remaining once in the preceding step effected and on each of the two opposite flanks of the same remaining furrow, thus forming the N + zones of the diodes; f) a metallic covering of all the furrows (3) of the complex structure of the preceding step; g) a withdrawal of the layer of polycrystalline silicon forming a support (18); and h) severing the assembly formed by several rods of silicon (11) effected at the level of the metallic coverings delimiting this assembly of rods, this permitting the production of a matrix of PIN diodes (5) in a series-parallel configuration.

Claim 11

The method as claimed in claim 6 characterized in that the deposit of a barrier layer (17) is performed by the thermal oxidation of the silicon substrate.