EP0140751A2
Expired / Lapsed
EP
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Cache invalidation mechanism for multiprocessor systems
Assignee: Digital Equipment Corp
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Filing: 1984-09-21
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Granted: —
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Expires: 2004-09-21
Abstract
Abstract In digital computer systems having one or more memory devices accessible to a number of separate system elements (50, 52) interconnected by a common communications path (08), one or more memory devices (54, 56) accessible by various elements without use of the common path, and one or more cache memories (190) storing local copies of data from the memory devices, the integrity of the cached data is preserved by notifying all cache devices (190) which may store data from a given memory element (54) of accesses to said element which do not take place along the common communications path.
Inventors
- 👤 Frank C. Bomba
- 👤 Dileep P. Bhandarkar
- 👤 J.J. Grady
- 👤 Stanley A. Lackey
- 👤 Jeffrey W. Mitchell
- 👤 Reinhard Schumann
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 16:14
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0833
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
98 words
For use in a digital computer system having a common communications path interconnecting a plurality of devices, including devices having local memory accessible without use of said path and cache memory for storing data communicated over said path from said local memory, the improvement which comprises a device which maintains the integrity of cached data, said device including: A. means for selectively registering accesses on said path to said local memory by devices having cached memory associated therewith, and B. means responsive to said registering means for notifying cached memory devices of non-path accesses to said local memory.
Claim 2
Dependent Claim
98 words
For use in a digital computer system having a common communications path interconnecting a plurality of devices, including devices having local memory accessible without use of said path and cache memory for storing data communicated over said path from said local memory, the improvement which comprises a device which maintains the integrity of cached data, said device including: A. means for selectively registering accesses on said path to said local memory by devices having cached memory associated therewith, and B. means responsive to said registering means for notifying cached memory devices of non-path accesses to said local memory.
Claim 3
Dependent Claim
58 words
A device according to claim 1 in which said registering means includes: (1) means for selectively distinguishing between local memory accesses which are to be following by data cacheing and accesses which are not, and (2) means enabling communication of said notification on said path only with respect to accesses which are to be followed by data cachinq.
Claim 4
Dependent Claim
53 words
A device according to claim 2 which includes: (1) means for generating a first set of read/write commands for memory accesses which are not to be followed by data cacheing, and (2) means for generating a second set. of read write commands for memory accessees which are to be followed by data cacheing.
References Cited (Backward Citations)
No citation records indexed.
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