Time shared translation buffer

Claim 2

A memory unit for use in a data processing system where the data processing system specifies memory locations with virtual addresses, the memory apparatus comprising, first and second virtual stores addressed by virtual addresses, a real store addressed by real addresses, a virtual-to-real translator for translating virtual addresses to provide real addresses, control means for causing said virtual-to-real translator to provide a translation whenever a real address corresponding to a virtual address is required.

Claim 3

- The apparatus of Claim 1 wherein said virtu - al-to-real translator includes first and second translation lookaside buffers corresponding to said first and second virtual stores, respectively, for storing real addresses corresponding to virtual addresses for said first and second virtual stores, respectively.

Claim 4

The apparatus of Claim 1 wherein said virtual-to-real translator includes a first translation lookaside buffer storing first entries relating virtual addresses to real addresses for said first virtual store, and includes a second translation lookaside buffer storing second entries storing subsets of the information stored in said first translation lookaside buffer.

Claim 5

The apparatus of Claim 3 including control means for accessing said second entries from said second translation lookaside buffer for sequential accesses to said second virtual store. .

Claim 7

The apparatus of Claim 4 further including, an address register for storing page addresses for addressing said second virtual store on page boundaries, page-boundary crossing means for sensing when a new page address in said address register is for a different page than the previous address in said address register to form a page-boundary crossing signal, control means for validating said second entries in response to a page boundary crossing signal.

Claim 8

The apparatus of Claim 3 further including, control means for accessing said second entries, validity sensing means for forming a validate signal, means for accessing said first entries in response to said validate signal.

Claim 9

The apparatus of Claim 7 wherein said validity sensing means includes means for determining when accesses to said second store are not sequential to thereby form said validate signal.

Claim 10

The apparatus of Claim 7 wherein said validity sensing means includes means for sensing an external signal to form said validate signal.

Claim 11

The apparatus of Claim 7 wherein said validity sensing means includes, address means for storing page addresses for addressing said second virtual store on page boundaries, page-boundary crossing means for sensing when a new page address in said address means is for a different page than the previous address in said address means to form said validate signal.

Claim 12

The apparatus of Claim 7 further including means for storing a subset of accessed first entries in said second translation lookaside buffer to provide new valid second entries.

Claim 13

The apparatus of Claim 1 wherein each addressable location said virtual-to-real translator includes a stored control field and wherein each virtual address includes an addressing control field, and further including a comparator for comparing the stored control field with the addressing control field to provide a match signal, control means for causing validation of the translation in the absence of a match signal.

Claim 14

The apparatus of -Claim 1 wherein said virtual-to-real translator includes translation lookaside buffer means for storing real addresses corresponding to virtual addresses for both said first and said second virtual stores.

Claim 15

The apparatus of Claim 1 wherein said virtual-to-real translator includes first and second translation lookaside buffers corresponding to said first and second virtual stores, respectively, for storing real addresses corresponding to virtual addresses, and further including means for using a translation provided by said first translation lookaside buffer for said first virtual store and for said second virtual store.

Claim 16

The apparatus of Claim 1 wherein said first virtual store stores operand information and wherein said second virtual store stores instruction information, an operand address register for addressing said first store, an instruction address register for addressing said second store, whereby accessing of operands from said first store and accessing of instructions in said second store is performed concurrently.

Claim 17

The apparatus of Claim 3 further including addressing means for providing a virtual address for addressing said first translation lookaside buffer and said second virtual store with the same virtual address.

Claim 18

The apparatus of Claim 1 wherein said virtual-to-real translator includes first and second translation lookaside buffers addressed by virtual addresses, and wherein said apparatus further includes ad- 'dressing means for providing first virtual addresses for addressing said first virtual store and said first translation lookaside buffer and for providing second virtual addresses for addressing said second translation lookaside buffer and said-second virtual store.

Claim 19

The apparatus of Claim 17 wherein said addressing means further includes means for providing a virtual address for addressing said first and second translation lookaside buffers and said first and second virtual stores with the same virtual address.

Claim 20

The apparatus of Claim 17 wherein said first and said second translation lookaside buffers each have addressable locations including a stored control field wherein said first and second virtual addresses include first and second addressing control fields, respectively, and said apparatus further including first and second comparators for comparing the first and second stored control fields with the first and second addressing control fields, respectively, to provide first and second control match signals.

Claim 21

The apparatus of Claim 1 wherein said virtual-to-real translator further includes first and second translation lookaside buffers storing first and second stored control fields, respectively, addressed by virtual addresses and wherein said first and second virtual stores include, first and second tag stores, respectively, storing first and second stored tag fields, respectively, addressed by virtual addresses, and further including first and second data arrays, respectively, for storing first and second data fields, respectively, addressed by virtual addresses, and further including addressing means for providing first and second virtual addresses for addressing said first and second virtual stores, said first and second translation lookaside buffers, respectively, said first and second virtual addresses having first and second addressing tag fields, respectively, and having first and second addressing control fields, respectively, first and second comparator means, said first comparator for comparing said first addressing tag field and said first addressing control field with said first stored tag field and said first stored control field, respectively, to provide a first match signal for indicating that the first data field is resident in said first virtual store, and said second comparator for comparing said second addressing tag field and said second addressing control field with said second stored tag field and said second stored control field, respectively, to provide a second match signal for indicating that the second data field is resident in the second.virtual store.

Claim 22

The apparatus of Claim 1 wherein said virtual-to-real translator further includes first and second translation lookaside buffers storing first and second stored control fields, respectively, addressed by virtual addresses and wherein said first and second virtual stores include, first and second tag stores, respectively, storing first and second stored tag fields, respectively, addressed by virtual addresses, and further including first and second data arrays, respectively, for storing first and second data fields, respectively, addressed by virtual addresses, and further including addressing means for providing first and second virtual addresses for addressing said first and second virtual stores, said first and second translation lookaside buffers, respectively, said first and second virtual addresses having first and second addressing tag fields, respectively, and having first and second addressing control fields, respectively, first and second comparator means, said first comparator for comparing said first addressing tag field and said first addressing control field with said first stored tag field and said first stored control field, respectively, to provide a first control match signal and a first tag match signal, respectively, and said second comparator for comparing said second addressing tag field and said second addressing control field with said second stored tag field and said second stored control field, respectively, to provide a second control match signal and a second tag match signal, respectively, whereby the presence of the first control match signal and a second tag match signal indicates that the second data field is resident in the.second virtual store,

Claim 23

The apparatus of Claim 21 wherein said second stored control field is a subset of said first stored control field.