EP0139126A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Phase-locked loops and electrical networks incorporating them
Assignee: British Telecommunications PLC
•
Filing: 1982-06-04
•
Granted: —
•
Expires: 2002-06-04
Abstract
Abstract A modification of a phase-locked loop comprises incorporating a variable delay element in the feedback path from the oscillator to the phase comparator. The delay is controlled by the signal at the input to the oscillator, and allows two phase-locked loops having different input delays to be interconnected and such that they stabilise at a common frequency. This arrangement may be used in a network of interconnected oscillator terminals to allow the terminals to synchronise even when only indirect paths exist between them. It is therefore highly fault tolerant.
Inventors
- 👤 Robert Mckenzie Falconer
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 04:00
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/07; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04J3/0635; H04J3/0676
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
74 words
A phase-locked loop characterised by the inclusion of a variable delay element from the output of its oscillator to the input of its phase comparator, the delay caused by the delay element being controlled by the signal that controls the oscillator so that when the oscillator is made to increase in frequency the delay is made to decrease and when the oscillator is made to decrease in frequency the delay is made to increase.
Claim 2
Dependent Claim
74 words
A phase-locked loop characterised by the inclusion of a variable delay element from the output of its oscillator to the input of its phase comparator, the delay caused by the delay element being controlled by the signal that controls the oscillator so that when the oscillator is made to increase in frequency the delay is made to decrease and when the oscillator is made to decrease in frequency the delay is made to increase.
Claim 3
Dependent Claim
25 words
A pair of phase-locked loops as claimed in Claim 1 characterised in that the output of each is connected to the input of the other.
Claim 4
Dependent Claim
168 words
A network of three or more phase-locked loops as claimed in Claim 1, each phase-locked loop being part of a terminal, and each terminal being interconnected each terminal further comprising reconfiguration control means operative to monitor the incoming signals to the terminal and to connect the phase-locked loop to any one of the incoming signals, the terminals being interconnected such that each is linked to the output of at least one of the other terminals in the network to receive output signals from the respective oscillators in those terminals; and the reconfiguration control means being operative to connect the phase-locked loop to any one of the incoming signals, if any are present, and to reconnect the phase-locked loop if the local oscillator fails to lock to the incoming signal initially chosen, the output from each oscillator being continuously transmitted on its outgoing links, so that the plurality of terminals tends toward stable synchronisation provided that a forward path exists directly or indirectly from anyone terminal to the remainder.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.