Interface arrangement for a telephone system or the like

Claim 2

An interface means (105) for applying information from a channel of a first digital bus (100a) to at least one processing circuit (117, 119) and for returning said information, after processing, to a respective channel, said means characterized by: converter means (101) for transforming the digital data on said first bus (100a) to digital data on a second digital bus (102); circuit means (103,113) for selectively accessing said second bus (102), under the control of a connection memory means (106, 116); said connection memory means responsive to timing signals (107,108) for controlling the access of said circuit means to said second bus such that said circuit means accesses said second bus at the appropriate time to receive the digital information from a selected channel on said second bus, and also accesses said bus at the appropriate time to transmit the digital information to a selected channel on said second bus.

Claim 3

The interface means of claim 1 wherein said second bus is a parallel bus.

Claim 4

The interface means of claim 1 wherein said second bus comprises two parallel buses (202a, 202b), each n bits wide, which can function both as two parallel buses, each n bits wide, or as one parallel bus, 2n bits wide.

Claim 5

An interface means (105) for applying information from a channel of a serial digital bus (100a) to at least one processing circuit (117 or 119) and for returning said information, after processing, to a respective channel, said means characterized by: serial to parallel converter means (101) for transforming the serial bits from said serial bus to parallel bits on a parallel digital bus (102); circuit means (103, 113) for selectively accessing said parallel bus, under the control of a connection memory means (106, 116); said connection memory means responsive to timing signals (107, 108) for controlling the access of said circuit means (103, 113) to said parallel bus such that said circuit means accesses said parallel bus (102) at the appropriate time to receive the digital information from a selected channel on said parallel bus, corresponding to said channel on said serial bus (100a), and also accesses said parallel bus (102) at the appropriate time to transmit the digital information to a selected channel on said parallel bus, corresponding to said channel on said serial bus.

Claim 6

An interface means (105) for applying information from a channel of a serial digital bus (100a) to at least one processing circuit (117 or 119) and for returning said information, after processing, to a respective channel, said means characterized by: serial to parallel converter means (101) for transforming the serial bits from said serial bus to parallel bits on a parallel digital bus (102); circuit means (103, 113) for selectively accessing said parallel bus, under the control of a connection memory means (106, 116); said connection memory means responsive to timing signals (107, 108) for controlling the access of said circuit means (103, 113) to said parallel bus such that said circuit means accesses said parallel bus (102) at the appropriate time to receive the digital information from a selected channel on said parallel bus, corresponding to said channel on said serial bus (100a), and also accesses said parallel bus (102) at the appropriate time to transmit the digital information to a selected channel on said parallel bus, corresponding to said channel on said serial bus.

Claim 7

The interface means (105) of claim 4 further including a parallel to serial converter means (124) for converting the digital information on said parallel bus to serial digital information on a serial bus (100b).

Claim 8

The interface means (205) of claim 5 further including a second parallel bus (202b), the output of said serial to parallel converter means (201) being applied to said first parallel bus (202a) and the input of said parallel to serial converter means (224) being responsive to said second parallel bus (202b), and said connection memory means (206, 216) controlling which of said two parallel buses is accessed at the appropriate time.

Claim 9

The interface means (205) of claim 4 further including a second parallel bus (202b), the output of said serial to parallel converter means (201) being applied to said first parallel bus 202a) and said connection memory means (206,216) controlling which of said two parallel buses is accessed at the appropriate time.

Claim 10

The interface means (105) of claim 4 wherein said serial to parallel converter means (253) includes a connection memory (250) and a data storage means (251).