EP0138439A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Electrically erasable programable nonvolatile semiconductor memory device having dual-control gate
Assignee: Toshiba Corp
•
Filing: 1984-09-24
•
Granted: —
•
Expires: 2004-09-24
Abstract
Abstract An electrically erasable programmable nonvolatile semiconductor memory device has a first semiconductor region (30) having a plurality of memory cells (10) arranged in a matrix form, a second semiconductor region (40) having a peripheral circuit for controlling the plurality of memory cells, an insulating region (42) for electrically insulating the first semiconductor region from the second semiconductor region, and a potential supply (Va) commonly applied to the data updating region (24) and the first semiconductor region when the data updating region exchanges a charge with a floating gate. Each memory cell has a floating gate (22), first and second control gates (18, 80) capacitively coupled to the floating gate (22), source and drain regions (14, 16) and the data updating region (24) contiguously formed with the source or drain region and exchanging the charge with the floating gate by a tunnel effect. The data updating region has a conductivity type opposite to the first semiconductor region. The first and second control gates of the respective memory cells are commonly connected and aligned along orthogonal directions in the matrix form.
Inventors
- 👤 Tadashi C/O Patent Division Shibata
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 21:02
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
229 words
An electrically erasable programable nonvolatile semiconductor memory device characterized by comprising: a first semiconductor region (30, 72, 82, 182) having a plurality of memory cells (10, 110) arranged in a matrix form, each of said plurality of memory cells having a floating gate (22, 122), first and second control gates (18, 118, 20, 120) capacitively coupled to said floating gate, source and drain regions (14, 114, 16, 116) and a data updating region (24, 124) formed contiguously with said source or drain region and exchanging a charge with said floating gate by a tunnel effect, said data updating region having a conductivity type opposite to that of said first semiconductor region, said first and second control gates of said plurality of memory cells being commonly connected, respectively, and arranged along orthogonal directions in the matrix form; a second semiconductor region (40, 74, 80, 180) having a peripheral circuit for controlling said plurality of memory cells (10, 110); insulating means (42, 60, 64, 70, 76, 81, 181) for electrically insulating said first semiconductor region (30, 72, 82, 182) from said second semiconductor region (40, 74, 80, 180); and potential sustaining means (Va, Vs) for sustaining said data updating region (24, 124) and said first semiconductor region (30, 72, 82, 182) at the same potential when said data updating region (24, 124) exchanges a charge with said floating gate (22, 122).
Claim 2
Dependent Claim
229 words
An electrically erasable programable nonvolatile semiconductor memory device characterized by comprising: a first semiconductor region (30, 72, 82, 182) having a plurality of memory cells (10, 110) arranged in a matrix form, each of said plurality of memory cells having a floating gate (22, 122), first and second control gates (18, 118, 20, 120) capacitively coupled to said floating gate, source and drain regions (14, 114, 16, 116) and a data updating region (24, 124) formed contiguously with said source or drain region and exchanging a charge with said floating gate by a tunnel effect, said data updating region having a conductivity type opposite to that of said first semiconductor region, said first and second control gates of said plurality of memory cells being commonly connected, respectively, and arranged along orthogonal directions in the matrix form; a second semiconductor region (40, 74, 80, 180) having a peripheral circuit for controlling said plurality of memory cells (10, 110); insulating means (42, 60, 64, 70, 76, 81, 181) for electrically insulating said first semiconductor region (30, 72, 82, 182) from said second semiconductor region (40, 74, 80, 180); and potential sustaining means (Va, Vs) for sustaining said data updating region (24, 124) and said first semiconductor region (30, 72, 82, 182) at the same potential when said data updating region (24, 124) exchanges a charge with said floating gate (22, 122).
Claim 3
Dependent Claim
94 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that said first semiconductor region (30) and said second semiconductor region (40) have the same conductivity type, and said insulating means comprises a third semiconductor region (42) formed at a boundary between said first semiconductor region and said second semiconductor region and having a conductivity type opposite to that of said first semiconductor region, said third semiconductor region being kept at the same potential as that of said first semiconductor region when said data updating region exchanges a charge with said floating gate.
Claim 4
Dependent Claim
37 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that said insulating means comprises an insulator (60, 62, 64) formed at a boundary between said first semiconductor region (30) and said second semiconductor region (40).
Claim 5
Dependent Claim
21 words
A nonvolatile semiconductor memory device according to claim 3, characterized in that said insulator (60, 64) comprises a silicon oxide layer.
Claim 6
Dependent Claim
30 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that said first semiconductor region (72) and said second semiconductor region (74) are fomred on said insulating substrate (70).
Claim 7
Dependent Claim
30 words
A nonvolatile semiconductor memory device according to claim 5, characterized in that said insulating substrate (70) comprises sapphire, and said first and second semiconductor regions (72, 74) comprise silicon islands.
Claim 8
Dependent Claim
35 words
A nonvolatile semiconductor memory device according to claim 6, characterized in that said insulating means comprises an insulator (76) formed at a boundary between said first semiconductor region (72) and said second semiconductor region (74).
Claim 9
Dependent Claim
20 words
A nonvolatile semiconductor memory device according to claim 7, characterized in that said insulator (76) comprises a silicon oxide layer.
Claim 10
Dependent Claim
101 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that said first semiconductor region (82) has a p conductivity type, said second semiconductor region (80) has an n conductivity type, and said first semiconductor region comprises a p-type well region formed in said second semiconductor region; said insulating means comprises a p-n junction (81) formed between said first semiconductor region and said second semiconductor region; and said potential sustaining means sets said data updating region and said first semiconductor region at the same negative potential when electrons are injected from said n-type data updating region to said floating gate.
Claim 11
Dependent Claim
52 words
A nonvolatile semiconductor memory device according to claim 9, characterized in that said potential sustaining means sets said data updating region (24) and said first semiconductor region (82) at a ground potential or the same positive potential when the electrons are emitted from said floating gate to said n-type data updating region.
Claim 12
Dependent Claim
101 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that said first semiconductor region (182) has an n conductivity type, said second semiconductor region (180) has a p conductivity type, and said first semiconductor region comprises an n-type well region formed in said second semiconductor region; said insulating means comprises a p-n junction (181) formed between said first semiconductor region and said second semiconductor region; and said potential sustaining means sets said data updating region and said first semiconductor region at the same positive potential when electrons are emitted from said floating gate to said n-type data updating region.
Claim 13
Dependent Claim
52 words
A nonvolatile semiconductor memory device according to claim 11, characterized in that said potential sustaining means sets said p-type data updating region (124) and said first semiconductor region (182) at a ground potential or the same negative potential when the electrons are injected from said data updating region to said floating gate.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.