Differential operational amplifier with common mode feedback

Claim 2

A differential operational amplifier having automatic means for controlling common mode output voltage levels, comprising: a differential operational amplifier for receiving two input signals and amplifying the difference, said operational amplifier having two input lines for receiving said two input signals and having two output lines for presenting the amplified difference between said two input signals; a feedback circuit connected to said two output lines of said differential operational amplifier, said feedback circuit including means for generating a reference voltage representative of the desired common mode feedback voltage, and further including means for comparing the instantaneous common mode voltage on said output lines with said reference voltage, the difference between said desired common mode voltage and said instantaneous common mode voltage constituting an error signal, said error signal being communicated on a feedback line to the differential operational amplifier to adjust the instantaneous common mode voltage towards the desired common mode voltage; and frequency compensation means in electrical communication with said feedback circuit and said differential operational amplifier to allow said error signal to possess negative feedback stability.

Claim 3

A differential operational amplifier in accordance with Claim 1 wherein said feedback circuit comprises: a first pair of MOS transistors having their sources connected to each other and to a first supply voltage line, the gates of said first pair of transistors being connected respectively to said two output lines of said differential operational amplifier, the drains of said first pair of transistors being connected together, the voltage on said drains having a value representative of the sum of the common mode voltage appearing on said two output lines; a second pair of MOS transistors having their sources connected together and to said first supply voltage line, the gates of each of said second pair of transistors being connected to a fixed voltage level which is representative of a desired common mode voltage level, the drains of each of said second pair of transistors being connected together, the voltages on said drains having a value of twice times the reference value for the common mode voltage; and current mirror means for receiving the current from said drains of said first pair of MOS transistors and mirroring the current from said drains of said first pair of transistors to the drains of said second pair of transistors; whereby the difference between said voltage on said drains of said first pair of MOS transistors and the voltage on said sources of said second pair of MOS transistors constitutes said error signal.

Claim 4

A differential operational amplifier in accordance with Claim 2 wherein said sources of said first pair of MOS transistors are connected to said first supply voltage line through a current supply transistor and wherein said sources of said second pair of MOS transistors are connected to said supply voltage line through a second current supply transistor.

Claim 5

A differential operational amplifier in accordance with Claim 2 wherein said sources of said first and second pairs of MOS transistors are connected to said first supply voltage line through the same current supply transistor.

Claim 6

A differential operational amplifier in accordance with Claim 2 wherein said first and second pair of MOS transistors comprise n-channel transistors.

Claim 7

A differential operational amplifier in accordance with Claim 2 wherein said first and second pairs of MOS transistors comprise p-channel transistors.

Claim 8

A differential operational amplifier in accordance with Claim 7 wherein the transistors in said differential operational amplifier and in said frequency compensation circuit are also p-channel transistors.

Claim 9

A differential operational amplifier in accordance with Claim 2 wherein the gates on each of said second pair of MOS transistors are connected to ground.

Claim 10

A differential operational amplifier in accordance with drain 2 wherein said current mirror means comprises a first MOS transistor having its drain connected to the coupled drains of said first pair of MOS transistors and a second MOS transistor having its drain connected to the coupled drains of said second pair of MOS transistors, the sources of said first and second MOS transistors being connected to a second voltage supply line, the gates of said first and second MOS transistors being interconnected.

Claim 11

A differential operational amplifier in accordance with drain 2 wherein said current mirror means comprises a first MOS transistor having its drain connected to the coupled drains of said first pair of MOS transistors and a second MOS transistor having its drain connected to the coupled drains of said second pair of MOS transistors, the sources of said first and second MOS transistors being connected to a second voltage supply line, the gates of said first and second MOS transistors being interconnected.

Claim 12

A differential operational amplifier in accordance with Claim 2 wherein said frequency compensation means comprises: a third MOS transistor whose gate is tied to one of said two output lines and whose source is connected to said first voltage supply line; a fourth MOS transistor whose gate is connected to the other of said two output lines and whose source is connected to said first voltage supply line; a first capacitor connected between the source of said third MOS transistor and an error signal feedback line; and a second capacitor connected between the source of said second transistor and the source of said error signal feedback line.

Claim 13

A differential operational amplifier in accordance with Claim 10 wherein the drains of said third and fourth MOS transistors are connected to said first voltage supply line through fifth and sixth MOS transistors, respectively, the gates of said fifth and sixth MOS transistors being connected to a fixed DC voltage bias level.