← Back to Patent Explorer
EP0137645A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method of forming a shallow N-type region

Assignee: Fujitsu Ltd
•
Filing: 1984-08-14
•
Granted: —
•
Expires: 2004-08-14
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of forming a shallow n-type region of a semiconductor device such as a bipolar transistor and a MOS FET, including the steps of: forming a first film (15) containing arsenic or antimony on a silicon substrate (11): forming a second film (18) containing phosphorus on the first film (15); and diffusing the arsenic or antimony and the phosphorus into the semi-conductor substrate (11) out of the first and second films by heat-treatment. The diffused impurities of the arsenic or antimony and the phosphorus form the n-type region (21) and the arsenic or antimony defines the depth of the n-type region (21).

Inventors

  • 👤 Katsunobu Ueno
  • 👤 Osamu Hataishi

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-30 20:12
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/34; H10D48/345; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 100 words
A method of forming a shallow n-type region (21) of a semiconductor device by introducing n-type impurities into a silicon semiconductor substrate (11), characterised by the steps of forming a first film (15) containing arsenic or antimony on the silicon substrate; forming a second film (18) containing phosphorus on the first film (15); and diffusing the arsenic or antimony and the phosphorus into the semiconductor substrate out of the first and second films (15,18) by heat-treatment, the arrangement being such that the diffusion depth of the arsenic or antimony is equal to or exceeds the diffusion depth of the phosphorus.
Claim 2
Independent Claim 100 words
A method of forming a shallow n-type region (21) of a semiconductor device by introducing n-type impurities into a silicon semiconductor substrate (11), characterised by the steps of forming a first film (15) containing arsenic or antimony on the silicon substrate; forming a second film (18) containing phosphorus on the first film (15); and diffusing the arsenic or antimony and the phosphorus into the semiconductor substrate out of the first and second films (15,18) by heat-treatment, the arrangement being such that the diffusion depth of the arsenic or antimony is equal to or exceeds the diffusion depth of the phosphorus.
Claim 3
Dependent Claim 32 words
A method according to claim 1, characterised in that the first film (15) and the second film (18) are made of polycrystalline silicon, amorphous silicon, or a silicide of platinum or tungsten.
Claim 4
Dependent Claim 39 words
A method according to claim 1 or claim 2, characterised in that arsenic or antimony is doped into the first film (15) by an ion-implantation method and phosphorus is doped into the second film (18) by an ion-implantation method.
Claim 5
Dependent Claim 51 words
A method according to claim 1 or claim 2, characterised in that arsenic or antimony is doped into the first film (15) during the formation thereof by a chemical vapour deposition method and phosphorus is doped into the second film (18) during the formation thereof by a chemical vapour deposition method.
Claim 6
Independent Claim 53 words
A method according to any of claims 1 to 3, wherein arsenic or antimony is doped into the first film (15) after the first film has been formed on the silicon substrate, and phosphorus is doped into the second film (18) after the second film has been formed on the first film (15).

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag