Patent US4003394A successfully refreshed from Google Patents.
EP0137564A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Integrated circuit comprising complementary field effect transistors
Assignee: Koninklijke Philips NV
•
Filing: 1984-10-04
•
Granted: —
•
Expires: 2004-10-04
Abstract
Abstract An integrated circuit comprising complementary field effect transistors (19A,20,21 and 19B,22,23), which are both of the normally-off depletion type. These transistors have in the channel region a surface layer (36,37) which has the same conductivity type as the adjoining source and drain zones (20,21 and 22,23). The surface layers (36,37) comprise per unit surface area a quantity of dopant which is at least equal to the charge per unit surface area in the part of the substrate region which adjoins the surface layer and which is depleted if between gate electrode and source and drain zones the threshold voltage is applied. The gate electrodes (19A,19B) comprise semiconductor material of opposite conductivity types.
Inventors
- 👤 François Marinus Klaassen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 03:15
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/637; H10D64/00; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
335 words
An integrated circuit comprising a semiconductor body having a major surface at which plural circuit elements are present, wherein the semiconductor body has near the major surface a first substrate region of a first conductivity type and a second substrate region of a second conductivity type, the first substrate region comprising a source and a drain zone of the second conductivity type of at least a first field effect transistor, a first channel region extending between these source and drain zones and at the major surface being covered by an insulating layer and wherein a first gate electrode comprising semiconductor material is present on this insulating layer, and the second substrate region comprising a source and a drain zone of the first conductivity type of at least a second field effect transistor, a second channel region extending between these source and drain zones and at the major surface being covered by an insulating layer and wherein a second gate electrode comprising semiconductor material is present on this insulating layer, the semiconductor material of the first gate electrode and the semiconductor material of the second gate electrode being of opposite conductivity types, characterized in that both in the first and in the second channel region between the said source and drain zones a surface layer adjoining the insulating layer links up with these zones, which surface layers are each of the same conductivity type as the adjoining source and drain zones, while the first and the second field effect transistor are both of the normally-off depletion type and moreover the quantity of dopant per unit surface area in each of the surface layers is at least equal to the quantity of charge per unit surface area in the part of the channel region which adjoins the surface layer and which is depleted if a voltage equal to the threshold voltage of the associated field effect transistor is applied to the associated gate electrode with respect to the source and drain zones of this field effect transistor.
Claim 2
Dependent Claim
335 words
An integrated circuit comprising a semiconductor body having a major surface at which plural circuit elements are present, wherein the semiconductor body has near the major surface a first substrate region of a first conductivity type and a second substrate region of a second conductivity type, the first substrate region comprising a source and a drain zone of the second conductivity type of at least a first field effect transistor, a first channel region extending between these source and drain zones and at the major surface being covered by an insulating layer and wherein a first gate electrode comprising semiconductor material is present on this insulating layer, and the second substrate region comprising a source and a drain zone of the first conductivity type of at least a second field effect transistor, a second channel region extending between these source and drain zones and at the major surface being covered by an insulating layer and wherein a second gate electrode comprising semiconductor material is present on this insulating layer, the semiconductor material of the first gate electrode and the semiconductor material of the second gate electrode being of opposite conductivity types, characterized in that both in the first and in the second channel region between the said source and drain zones a surface layer adjoining the insulating layer links up with these zones, which surface layers are each of the same conductivity type as the adjoining source and drain zones, while the first and the second field effect transistor are both of the normally-off depletion type and moreover the quantity of dopant per unit surface area in each of the surface layers is at least equal to the quantity of charge per unit surface area in the part of the channel region which adjoins the surface layer and which is depleted if a voltage equal to the threshold voltage of the associated field effect transistor is applied to the associated gate electrode with respect to the source and drain zones of this field effect transistor.
Claim 3
Dependent Claim
33 words
An integrated circuit as claimed in Claim 1, characterized in that the first and the second field effect transistor each have a channel length which is smaller than 3 / , M .
Claim 4
Dependent Claim
38 words
An integrated circuit as claimed in Claim 1 or 2, characterized in that both in the first and in the second field effect transistor the ratio between the channel width and the channel length is at least 2..
Claim 5
Dependent Claim
52 words
An integrated circuit as claimed in any one of the preceding Claims, characterized in that both in the first and in the second field effect transistor the conductivity type of the semiconductor material of the gate electrode is opposite to the conductivity type of the subjacent surface layer of the channel region.
Claim 6
Dependent Claim
58 words
An integrated circuit as claimed in any one of the preceding Claims, characterized in that the first and the second gate electrode are directly connected to each other, the semiconductor material of the first gate electrode, whilst forming a junction, adjoining the semiconductor material of the second gate electrode and this junction being shunted by a conductive connection.
Claim 7
Dependent Claim
51 words
An integrated circuit as claimed in any one of the preceding Claims, characterized in that the first and the second gate electrode each have a silicide top layer, which silicide top layer is separated by the semiconductor material of the gate electrode from the insulating layer located under the gate electrode.
Claim 8
Dependent Claim
27 words
An integrated circuit as claimed in Claim 6, characterized in that the first and the second gate electrode consist over at moast half their thickness of silicide.
Claim 9
Dependent Claim
78 words
An integrated circuit as claimed in any one of the preceding Claims, characterized in that both in the first and in the second field effect transistor the pn junction between the surface layer and the substrate region formed in the channel region is located at a depth under the semiconductor surface which is at least half the depth of the least deeply located pn junctions between the source and drain zones and the substrate region adjoining these zones.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.