Method of and device for the digital cancellation of the echo generated in connections with time-varying characteristics

Claim 2

Method of digital cancellation of echo generated in connections with characteristics quickly varying in time, comprising the steps of copying a pulse response of the equivalent echo channel by an adaptive digital transversal filter, with M taps, which receives digital samples x(k) of the echo generating signal, k being the discretized time variable, iteratively updated coefficients h(m), m(0≤m≤M) being the index of the m-th filter tap, and which supplies samples z(k) of the echo-signal estimate signal, subsequently subtracted from an echo-affected signal, also comprising the steps of crosstalk detecting as well as residual-echo silencing, characterized in that said pulse response is subdivided into three intervals, the first (Tl) consisting of flat-delay, the second (T2) being the significant response portion, the third (T3) being generated by low frequencies with values outside the voice band, in that an estimate of the iterative type is made of the position of said second interval, considered of fixed lenght, and in that for determining said samples z(k) of the estimate signal there are considered only coefficients h(m) whose index m falls within said second interval, and samples x(k) of preceding instants k-m, with respect to the present instant k, whose index m falls within said second interval, characterized also in that only the updating is effected of coefficients h(m) whose index m is comprised inside the second interval.

Claim 3

Method according to claim 1, characterized in that said estimate of the position of the second interval (T2) is carried out by means of an iterative procedure in which: - the coefficients are examined having an index comprised in the second interval determined at the preceding iteration, starting at the first iteration from a fictitious condition corresoponding to a null flat delay, and the coefficient is looked for having the maximum alsolute value, whose index m=W MAX is taken as a reference; - an integer fixed number from value W MAX is subtracted, obtaining a value m=W which is set to zero if from the subtraction it comes out m<0 or m > M-N, said value W being considered as index of the first coefficient of the second interval; - an integer fixed number N-1 is added to value W, thus obtaining a value m=W+N-1 considered as index of the last coefficient of the second interval, N being the number of actual taps of the transversal filter.

Claim 4

Method according to claim 1 or 2, characterized in that a filtering of the pass-band type is effected on said signal which generated the echo before converting said signal into a sequence of the digital samplesx(k), thus eliminating low frequencies generating said third interval (T3).

Claim 5

Method according to claim 2 or claim 3 referred to claim 2, characterized in that, at each iteration of estimate of the position of said second interval (T2), the coefficients are reset to zero whose index is comprised in the second interval determined in the present iteration and not comprised in that determined at the preceding iteration.

Claim 6

Device for the digital echo cancellation for implementing the method of any of the preceding claims, consisting of a micropro- grammes unit comprising a control unit (MUX1, SEQ, ROMP, PIPE), a computing unit (MAC), random access data memories (RAMA, RAM1, RAM2) and a read only memory (ROMC) containing determined constant values, said memories being addressed by programmable up/down counters (CT1, CT2, CT3) connected to an address bus (ADRB), and data input/output devices (RU, MUX2) connected to an internal bus (BUSP), characterized in that a first one (RAM1) of the data memories stores said coefficients h(m) present on said internal bus (BUSP) and supplies them onto a first input bus (BF1) of said computing unit (MAC), a second one (RAM2) of the data memories implements the transversal-filter delay-line, and keeps the last M samples x(k) present on said internal bus (BUSP) and coming from the input device (MUX2) and supplies them onto a second input bus (BF2) of said computing unit (MAC), a third one (RAMA) of the data memories stores determined bit configurations present on said address bus (ADRB), the output of said computing unit being connected to said internal bus (BUSP), which can be connected to said address bus by a bidirectional receiver (PAI); also characterized in that to determine said second interval (T2) there are read in said first memory (RAM1) the coefficients whose index is comprised in said second interval determined at the preceding iteration, and a maximum absolute value determined in the preceding iteration, said maximum absolute value being stored in a first register (RD) connected to said first input bus (BF1), and said computing unit (MAC) computes for each of said coefficients the difference between its absolute value and said maximum absolute value, and if said difference is positive, it writes in said first memory (RAM1), through a second register (RF1), which connects said internal bus (BUSP) with said first input bus (BF1), the absolute value of said coefficient in the positiom of said maximum absolute value, and in said third data memory (RAMA) the difference (DH) between the addresses of the first coefficient of the second interval (T2) and of said coefficient, said difference (DH) being the counting value attained by a programmable counter (CT2) incremented by a unit at each coefficient examined, and programmed at the negative value equal to the difference between the address of the first coefficient and the address of the maximum-value coefficient of said second interval; and when all the coefficients of the second interval have been examined, said computing unit (MAC) effects the addition between the address of said first coefficient, and the value of said difference (DH), read in said third memory (RAMA) and transferred onto said first (BF1) and respectively second (BF2) input bus through the second (RF1) and a third (RF2) register connected to said internal bus (BUSP), and writes the result of said addition in said third memory (RAMA) as an address of the first coefficient of the new second interval thus determined, then it carries out the addition between the address of sample x(k-W), stored in said third data memory (RAMA) and transferred though said third register (RF2) on said second input bus (BF2), and said difference (DH), and writes the result in said third memory (RAMA), at the place of the preceding result, as a new address of sample x(k-W); also characterized in that if the result of the addition carried out by said computing unit (MAC) between the address of said first coefficient and the value of said difference (DH) is negative, or greater than W-N, there are written in said third memory (RAMA) the address of coefficients h(0) as an address of the first coefficient of the new second interval, and the address of sample x(k) as anew address of sample x(k-W).

Claim 7

Device as in claim 5, characterized in that, after the execution of said additions by the computing unit (MAC), there are reset to zero the positions of said first memory (RAM1) corresponding to the coefficients whose index is comprised in the new second interval, while it was not in the preceding one.