EP0137481A2
Expired / Lapsed
EP
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Image processing system
Assignee: Hitachi Ltd
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Filing: 1984-10-09
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Granted: —
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Expires: 2004-10-09
Abstract
Abstract An area designating memory (22) for storing a bit pattern representing a picture designating area used for image processing, and a video memory (11) for storing an image to be image-processed in a form of digital picture element data are provided in an image processing system. In synchronism with picture element address signals (13, 14) sequentially generated by an address generating circuit (16), corresponding picture element data is read from the video memory, and also, corresponding area designating bits are sequentially read from the area designating memory. The read picture element data and associated area designating bit are applied to a logic-arithmetic circuit (36), and the read picture element data is selectively gated depending on the status of the area designating bit. The video memory (11) and area designating memory (22) may be read/written by an external processor (100). By manipulating a video signal switching circuit (7), the digitized video signal is directly gated depending on the status of the area designating bit read from the area designating memory (22), and thus the processed image signal can also be obtained without the video memory.
Inventors
- 👤 Makoto Ariga
- 👤 Shunji Maeda
- 👤 Seiji Hata
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 21:54
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/60
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
158 words
An image processing system comprising: a signal input section (42) for accepting a digitized video signal (4) to be image processed, said video signal being constituted by a plurality of digital picture element data; an area designating memory (22) for storing digital data to designate a picture area for image processing with respect to an image represented by said video signal; address generating means (16, 20, 21) for providing to said area designating memory a picture element address corresponding to each digital picture element data in synchronism with the each digital picture element data in said digitized video signal, and for reading area designating digital data corresponding to the picture element data; and a signal output section (40, 41) including a control signal line for transferring the area designating digital data read from said area designating memory as a control signal (35) for image processing and including an output signal line for transferring said digitized video signal (4a).
Claim 2
Dependent Claim
158 words
An image processing system comprising: a signal input section (42) for accepting a digitized video signal (4) to be image processed, said video signal being constituted by a plurality of digital picture element data; an area designating memory (22) for storing digital data to designate a picture area for image processing with respect to an image represented by said video signal; address generating means (16, 20, 21) for providing to said area designating memory a picture element address corresponding to each digital picture element data in synchronism with the each digital picture element data in said digitized video signal, and for reading area designating digital data corresponding to the picture element data; and a signal output section (40, 41) including a control signal line for transferring the area designating digital data read from said area designating memory as a control signal (35) for image processing and including an output signal line for transferring said digitized video signal (4a).
Claim 3
Dependent Claim
73 words
An image processing system according to claim 1, further comprising: a video memory (11) capable of writing and reading, in synchronism with a picture element address from said address generating means, digital picture element data corresponding to the picture element address of said digitized video signal; and a first signal switching circuit (7) connected to said signal input section, said output signal line and said video memory for switching signal paths connected therebetween.
Claim 4
Dependent Claim
220 words
3 . An image processing system according to claim 2, further comprising: an external address setting register for holding data for providing a picture element address externally to said video memory and said area designating memory; a data bus for writing and reading data externally from said video memory and said area designating memory; a first address switching means (12) for switching between picture element address from said address generating means and picture element address from said address setting register and for providing to said video memory the switched picture element address; a second address switching means (21) for switching between picture element address from said address generating means and picture element address from said address setting register and for providing to said area designating memory the switched picture element address; a second signal switching circuit (28) connected to said area designating memory, said control line and said data bus for switching signal paths connected therebetween; and external setting register means connected to said first and second address switching means and said first and second signal switching circuits for holding data to control externally the operations thereof; wherein said first signal switching circuit is also connected to said data bus, and switching of signal paths between said data bus, said video memory and said signal input section is also enabled.
Claim 5
Dependent Claim
38 words
An image processing system according to claim 1, further comprising: logic-arithmetic means (36) connected to said signal output section for generating an image processed signal (37) by processing said digitized video signal in response to said control signal.
Claim 6
Dependent Claim
18 words
An image processing system according to claim 4, wherein said logic-arithmetic means includes a plurality of AND gates.
Claim 7
Dependent Claim
32 words
An image processing system according to claim 1, further comprising: an A/D converting circuit (2) connected to said signal input section for converting an analog video signal into said digitized video signal.
Claim 8
Dependent Claim
43 words
An image processing system according to claim 2, wherein said video memory (11) and said area designating memory (22) are formed integrally as a unit, and read/write data to said both memories consists of digital picture element data and area designating digital data.
Claim 9
Dependent Claim
33 words
An image processing system according to claim 1, further comprising: logic·arithmetic means (36a) connected between said input section and said video memory for processing said digitized signal in response to said control signal.
Claim 10
Dependent Claim
19 words
An image processing system according to claim 8, wherein said logic·arithmetic means (36a) includes a plurality of AND gates.
Claim 11
Dependent Claim
38 words
An image processing system according to claim 1, wherein the area designating digital data of said area designating memory (22) is formed by a plurality of area designating bits capable of area designation of a plurality of pictures.
Claim 12
Dependent Claim
49 words
An image processing system according to claim 10, further comprising: an area picture selecting circuit (30) connected to said control signal line and said area designating memory for producing a control signal by selecting area designating bits representing one desired picture out of a plurality of area designating pictures.
Claim 13
Dependent Claim
57 words
An image processing system according to claim 10, further comprising: an area picture selecting circuit (30) connected to said control signal line and said area designating memory for selecting area designating bits representing at least two pictures out of a plurality of area designating pictures and for producing a control signal by logic processing the selected bits.
References Cited (Backward Citations)
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