A semiconductor memory having multiple access

Claim 2

A semiconductor memory comprising, a memory array of memory cells arranged in rows and columns, a first access circuit responsive to row and column address signals and a read-write control signal for selectively writing data into and reading data out of memory cells of said memory array addressed by said address signals, and a second access circuit responsive to a second set of row and column address signals for reading data from memory cells of said memory array defined by said second set of row and column address signals.

Claim 3

The invention as claimed in claim 1, wherein said semiconductor memory is formed on a semiconductor chip.

Claim 4

The invention as claimed in claim 1, wherein said memory array includes first word lines, second word lines, first digit lines arranged vertically to said first word lines, and second digit lines arranged vertically to said second word lines, said first word lines and said first digit lines being adapted to be connected to said first access circuit, said second word lines and said second digit lines being adapted to be connected to said second access circuit.

Claim 5

The invention as claimed in claim 3, wherein each of said memory cells includes first and second capacitance means, each having one end connected to a fixed potential line, a first field effect transistor coupled between the other end of said first capacitance means and the associated one of said first digit lines and having a gate coupled with the associated one of said first word lines, a series circuit of second and third field effect transistors coupled between the other end of said first capacitance means and the other end of said second capacitance means, the gate of said second field effect transistor being connected to said associated one of said first word lines, the gate of said third field effect transistor being supplied with a write selection signal, and a fourth field effect transistor coupled between the other end of said second capacitance means and the associated one of said second digit lines and having a gate coupled to the associated one of said second word lines.

Claim 6

The invention as claimed in claim 1, further comprising first control means for operatively inhibiting said second access circuit from reading data from a memory cell of said memory array when both of said first and second access circuits simultaneously address said memory cell for a write operation and a read operation, respectively.

Claim 7

The invention as claimed in claim 1, further comprising, means for detecting when said first and second access circuits simultaneously address in the same row of a write and read operation, respectively, and means responsive to said detecting means for maintaining active the write operation of said first access means until a short period of time following termination of the read operation of said second access circuit.

Claim 8

The invention as claimed in claim 1, wherein, said first access circuit includes a first bus line and a plurality of first transfer gates coupled between said first bus line and a plurality of said first digit lines, respectively; said second access circuit includes a second bus line and a plurality of second transfer gates coupled between said second bus line and a plurality of said second digit lines, respectively; further comprising, a plurality of third transfer gates coupled between said first bus and said plurality of second digit lines, and control means for selectively enabling one of said third transfer gates when said first and second access circuits designate the same row address and said first access circuit performs a write operation.

Claim 9

A semiconductor memory comprising first word lines, first digit lines arranged vertically with respect to said first word lines, second word lines, second digit lines arranged vertically with respect to said second word lines, and a plurality of memory cells, each of said memory cells including a first capacitor means having one end connected to a fixed potential line, a second capacitor means having one end connected to said fixed potential line, a first field effect transistor coupled between the other end of said first capacitor means and the associated one of said first digit lines and having a gate coupled to the associated one of said first word lines, a series circuit of second and third field effect transistors coupled between the other end of said first capacitor means and the other end of said second capacitor means, the gate of said second transistor being connected to said associated first word line, the gate of said third transistor being supplied with a selec- tional write signal, and a fourth field effect transistor coupled between the other end of said second capacitor means and the associated one of said second digit lines and having a gate coupled to the associated one of said second word line.

Claim 10

A semiconductor memory comprising first word lines, first digit lines arranged vertically with respect to said first word lines, second word lines, second digit lines arranged vertically with respect to said second word lines, and a plurality of memory cells, each of said memory cells including a first capacitor means having one end connected to a fixed potential line, a second capacitor means having one end connected to said fixed potential line, a first field effect transistor coupled between the other end of said first capacitor means and the associated one of said first digit lines and having a gate coupled to the associated one of said first word lines, a series circuit of second and third field effect transistors coupled between the other end of said first capacitor means and the other end of said second capacitor means, the gate of said second transistor being connected to said associated first word line, the gate of said third transistor being supplied with a selec- tional write signal, and a fourth field effect transistor coupled between the other end of said second capacitor means and the associated one of said second digit lines and having a gate coupled to the associated one of said second word line.

Claim 11

The invention as claimed in claim 4, further comprising first control means for operatively inhibiting said second access circuit from reading data from a memory cell of said memory array when both of said first and second access circuits simultaneously address said memory cell for a write operation and a read operation, respectively.

Claim 12

The invention as claimed in claim 4, further comprising, means for detecting when said first and second access circuits simultaneously address in the same row of a write and read operation, respectively, and means responsive to said detecting means for maintaining active the write operation of said first access means until a short period of time following termination of the read operation of said second access circuit.

Claim 13

The invention as claimed in claim 4, wherein said first access circuit includes a first bus line and a plurality of first transfer gates coupled between said first bus line and a plurality of said first digit lines, respectively; said second access circuit includes a second bus line and a plurality of second transfer gates coupled between said second bus line and a plurality of said second digit lines, respectively; further comprising, a plurality of third transfer gates coupled between said first bus and said plurality of second digit lines, and control means for selectively enabling one of said third transfer gates when said first and second access circuits designate the same row address and said first access circuit performs a write operation.

Claim 14

The invention as claimed in claim 9, further comprising, means for detecting when said first and second access circuits simultaneously address in the same row of a write and read operation, respectively, and means responsive to said detecting means for maintaining active the write operation of said first access means until a short period of time following termination of the read operation of said second access circuit.

Claim 15

The invention as claimed in claim 12, wherein said first access circuit includes a first bus line and a plurality of first transfer gates coupled between said first bus line and a plurality of said first digit lines, respectively; said second access circuit includes a second bus line and a plurality of second transfer gates coupled between said second bus line and a plurality of said second digit lines, respectively; further comprising, a plurality of third transfer gates coupled between said first bus and said plurality of second digit lines, and control means for selectively enabling one of said third transfer gates when said first and second access circuits designate the same row address and said first access circuit performs a write operation.