EP0136952A2
Expired / Lapsed
EP
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A gate array
Assignee: Fujitsu Ltd
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Filing: 1984-09-28
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Granted: —
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Expires: 2004-09-28
Abstract
Abstract A gate array having a plurality of basic cells (12) each comprising a transistor whose gm is as low as one fifth to one twentieth of the gm of the transistors in the conventional gate array is disclosed. The low gm is provided by reducing the W/L ratio of the gate region of the transistor. The basic cell (12) comprising the transistor of the low gm is formed to replace the conventional basic cell at a specified position in a specified basic cell array 400. The transistor of low gm reduces the basic cells necessary for constituting a delay circuit, and eliminates need for the external resistive component which is formerly requisite when a pull-up or pull-down circuit or a monostable multivibrator is built in the gate array.
Inventors
- 👤 Hideo Monma
- 👤 Masato Ishiguro
- 👤 Tetsuo Kawano
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 22:02
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/0165; H10D84/0193
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
117 words
A gate array formed in a semiconductor substrate chip having an inner region (10) and an outer region (13), characterized in that said gate array comprises : a plurality of first basic cells (11) each including a transistor having relatively higher gm; and a plurality of second basic cells (12) each including a transistor having relatively smaller gm; wherein said first basic cells (11) form a plurality of basic cell arrays (400) disposed in parallel to one another in the inner region (10) of said semiconductor substrate chip (300), and each of said second basic cell (12) is formed to replace said first basic cell (11) at each of specified positions in said basic cell arrays (400).
Claim 2
Dependent Claim
117 words
A gate array formed in a semiconductor substrate chip having an inner region (10) and an outer region (13), characterized in that said gate array comprises : a plurality of first basic cells (11) each including a transistor having relatively higher gm; and a plurality of second basic cells (12) each including a transistor having relatively smaller gm; wherein said first basic cells (11) form a plurality of basic cell arrays (400) disposed in parallel to one another in the inner region (10) of said semiconductor substrate chip (300), and each of said second basic cell (12) is formed to replace said first basic cell (11) at each of specified positions in said basic cell arrays (400).
Claim 3
Dependent Claim
39 words
A gate array as set forth in claim 1, characterized in that the ratio of gate width (W) to gate length (L) in the transistor in said second basic cell (12) is in the range from 0.5 to 2.
Claim 4
Dependent Claim
34 words
A gate array as set forth in claim 1, characterized in that said second basic cell (12) comprises a pair of a p-channel transistor (P 3 ) and an n-channel transistor (N 3 ).
Claim 5
Dependent Claim
76 words
A gate array as set forth in claim 1, characterized in that said second basic cell (12) comprises two pairs (P 4 ,N 4 ; P 5 , N 5 ) of a p-channel transistor (P 4 ;P 5 ) and an n-channel transistor (N,;N 5 ), said pairs being arranged in parallel to each other, and the p-channel and n-channel transistors in each said pair being arranged so that their gates are aligned in line.
Claim 6
Dependent Claim
56 words
A gate array as set forth in claim 3 or 4, characterized in that the ratio of gm of the p-channel transistor (P3; P4,P5) to gm of the n-channel transistor (N 3 ; N 4 , N 5 ) in said pair in said second basic cell (12) is in the range from 0.5 to 2.
Claim 7
Dependent Claim
61 words
A gate array as set forth in claim 3 or 4, characterized in that the gate electrode (20, 21; 26,27) of each of p-channel and n-channel transistors in said second basic cell (12) is widened at the portion of the gate relatively to the gate length, and the p-channel and n-channel transistors are staggered in the direction along their gate lengths.
Claim 8
Dependent Claim
66 words
A gate array as set forth in claim 3 or 4, characterized in that the gates of the p-channel (P 4 ; P 5 ) and n-channel transistors (N 4 ; N 5 ) in each said pair ( P 4' N 4 ; P 5' N 5 ) are connected each other by the same electrode material to form a single common gate (26; 27).
Claim 9
Dependent Claim
21 words
A gate array as set forth in claim 1, characterized in that said second basic cell (12) constitutes a delay circuit.
Claim 10
Dependent Claim
63 words
A gate array as set forth in claim 1, characterized in that it further comprises a plurality of input/output cells (15) formed in the peripheral region of the semiconductor substrate chip (33), wherein said input/output cells (15) constitute input/output circuits, and said second basic cell (12) is used for constituting a pull-up or pull-down circuit (5 0 0) for a specified input/output circuit.
References Cited (Backward Citations)
No citation records indexed.
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