EP0136771A2
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EP
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A nonvolatile semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1984-05-23
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Granted: —
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Expires: 2004-05-23
Abstract
Abstract in a nonvolatile semiconductor memory device having a matrix of electrically erasable and programmable memory cells (M1 - M4) each of which has a floating gate, an erase gate, and two control gates, a relationship among the potentials selectively applied to the floating gate, the erase gate, and the two control gates is preset to decrease changes in the threshold level of the half-selected memory cells, thereby achieving high reliability. In the writing mode, a voltage of +25 V is applied to the selected row and column control lines (CG21, CG11), a first low voltage of 0 V is applied to the remaining row and column control lines (CG22, CG12), and a second low voltage of +5 V is applied to a source control line (S1, S2). In the erasing mode, a low voltage of 0 V is applied to the selected row and column control lines (CG21, CG11), a first high voltage of +25 V is applied to the remaining row and column control lines (CG22, CG12), and a second high voltage of +20 V is applied to the source control line (S1, S2).
Inventors
- 👤 Masaki C/O Patent Division Momodomi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 05:38
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/32; H; H10; H10D; H10D30/00; H10D30/60
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
313 words
A nonvolatile semiconductor memory device having a plurality of memory cells of a MOSFET structure which are arranged in a matrix form, each memory cell being formed on a semiconductor substrate (1) and having a floating gate (5) electrically insulated from any other component, first and second control gates (6, 7) capacitively coupled to said floating gate (5), and an erase gate (8) for exchanging carriers with said floating gate (5) by a tunnel effect, said first and second control gates (6, 7) of the respective memory cells being commonly connected as a plurality of column control lines (CG11, CG12) and a plurality of row control lines (CG21, CG22) extending along orthogonal directions, respectively, said erase gates (5) of the respective memory cells being connected as a source control line (Sl, S2) common for all bits or in units of a plurality of blocks, writing being performed such that a high voltage is applied to selected row and column control lines of said row and column control lines, a first low voltage is applied to nonselected row and column lines thereof, and a second low voltage is applied to said source control line, erasing being performed such that a low voltage is applied to selected row and column control lines, a first high voltage is applied to nonselected row and column control lines, and a second high voltage is applied to said source control line, characterized in that said nonvolatile semiconductor memory device comprises circuit means for selecting at least one of a writing mode, wherein the second low voltage applied to said source control line is higher than the first low voltage applied to said nonselected row and column control lines, and an erasing mode, wherein the first high voltage applied to said nonselected row and column control lines is higher than the second high voltage applied to said source control line.
Claim 2
Dependent Claim
313 words
A nonvolatile semiconductor memory device having a plurality of memory cells of a MOSFET structure which are arranged in a matrix form, each memory cell being formed on a semiconductor substrate (1) and having a floating gate (5) electrically insulated from any other component, first and second control gates (6, 7) capacitively coupled to said floating gate (5), and an erase gate (8) for exchanging carriers with said floating gate (5) by a tunnel effect, said first and second control gates (6, 7) of the respective memory cells being commonly connected as a plurality of column control lines (CG11, CG12) and a plurality of row control lines (CG21, CG22) extending along orthogonal directions, respectively, said erase gates (5) of the respective memory cells being connected as a source control line (Sl, S2) common for all bits or in units of a plurality of blocks, writing being performed such that a high voltage is applied to selected row and column control lines of said row and column control lines, a first low voltage is applied to nonselected row and column lines thereof, and a second low voltage is applied to said source control line, erasing being performed such that a low voltage is applied to selected row and column control lines, a first high voltage is applied to nonselected row and column control lines, and a second high voltage is applied to said source control line, characterized in that said nonvolatile semiconductor memory device comprises circuit means for selecting at least one of a writing mode, wherein the second low voltage applied to said source control line is higher than the first low voltage applied to said nonselected row and column control lines, and an erasing mode, wherein the first high voltage applied to said nonselected row and column control lines is higher than the second high voltage applied to said source control line.
Claim 3
Dependent Claim
141 words
A device according to claim 1, characterized in that said memory cell comprises: source and drain regions (3, 4) of n +- layers formed on a p-type silicon substrate (1); said floating gate (5) formed on a channel region between said source and drain regions (3, 4) through a gate insulating film; first and second control gates (6, 7) sequentially formed on said floating gate (5) through another gate insulating film; and an erase gate (8) which is formed adjacent to the channel region of said substrate (1) so as to be connected to said source region (3) and which comprises an n + -layer overlapping said floating gate (5) through a thin gate insulating film, and in that the voltages selectively applied to said source control line and said row and column control lines are 0 V or positive voltages.
Claim 4
Dependent Claim
140 words
A device according to claim 1, characterized in that said memory cell comprises: source and drain regions (3, 4) of p +- layers formed on an n-type silicon substrate (1); said floating gate (5) formed on a channel region between said source and drain regions (3, 4) through a gate insulating film; first and second control gates-(6, 7) sequentially formed on said floating gate (5) through another gate insulating film; and an erase gate (8) which is formed adjacent to the channel region of said substrate (1) so as to be connected to said source region (3) and which comprises an p +- layer overlapping said floating gate (5) through a thin gate insulating film, and in that the voltages selectively applied to said source control line and said row and column control lines are 0 V or negative voltages.
Claim 5
Dependent Claim
25 words
A device according to claim 1, characterized in that said floating gate (5) and said first and second control gates (6, 7) comprise doped-polycrystalline silicon.
Claim 6
Dependent Claim
50 words
A device according to claim 1, characterized in that said memory cell is constructed such that said floating gate (5) has an offset structure so as to cover a central portion of the channel region and that said second control gate (7) covers a remaining portion of the channel region.
References Cited (Backward Citations)
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