EP0136182A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Multi level pipeline control store for cpu microsequencing
Assignee: Tandem Computers Inc
•
Filing: 1984-09-28
•
Granted: —
•
Expires: 2004-09-28
Abstract
Abstract The control store for a central processing unit is divided into two portions, a horizontal portion and a vertical portion. The vertical control store portion contains the information for the first phase of the pipeline as well as an address which is registered and used to address the horizontal control store portion which contains the second and later pipeline stage information. Multiple vertical control store portions share a common horizontal control store portion line resulting in compression.
Inventors
- 👤 Robert Whiting Horst
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 13:18
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/223
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
163 words
A control store for storing microcode for use in implementing a set of microinstructions in a pipelined central processing unit of a data processing system characterised by the combination of a vertical portion (18) having a plurality of storage locations addressed by a set of inputs, each of said storage locations holding a decoded first rank (12) of microcode and an encoded vector to a decoded second rank (14) of microcode for a particular one of said set of microinstructions, said encoded vector and said first rank (l2) of microcode appearing on separate sets of output lines in response to information on said set of inputs, and a horizontal portion (28) having a plurality of storage locations addressed by a set of inputs, the latter inputs being supplied with said encoded vector on one set of output lines (26) from said vertical portion (18), and said horizontal portion (28) supplying on a set of output lines said decoded second rank (14) of microcode.
Claim 2
Dependent Claim
163 words
A control store for storing microcode for use in implementing a set of microinstructions in a pipelined central processing unit of a data processing system characterised by the combination of a vertical portion (18) having a plurality of storage locations addressed by a set of inputs, each of said storage locations holding a decoded first rank (12) of microcode and an encoded vector to a decoded second rank (14) of microcode for a particular one of said set of microinstructions, said encoded vector and said first rank (l2) of microcode appearing on separate sets of output lines in response to information on said set of inputs, and a horizontal portion (28) having a plurality of storage locations addressed by a set of inputs, the latter inputs being supplied with said encoded vector on one set of output lines (26) from said vertical portion (18), and said horizontal portion (28) supplying on a set of output lines said decoded second rank (14) of microcode.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.