Wafer fabrication by implanting through protective layer

Claim 1

A method for fabricating a bipolar substantially isoplanar integrated circuit structure on a substrate of semiconductor material of a first conductivity type, said substrate being processed by depositing an epitaxial layer (15) of semiconductor material over the substrate thereby forming an isolation junction extending laterally through the structure between the epitaxial layer and sustrate, forming a thin epitaxial oxide buffer layer (16) over the epitaxial layer, subdividing said structure into a plurality of epitaxial islands (25) in which active and passive elements are fabricated, and isolating said epitaxial islands relative to each other by forming annular shaped isolation oxide regions (22) of oxidized semiconductor material extending through the epitaxial layer to the isolation junction, characterized in that the method comprises : depositing a uniform nitride layer (28) over the structure thereby passivating the structure and protecting the isolation oxide regions, epitaxial oxide buffer layer and epitaxial layer from contaminants; implanting collector sink regions (30) in the epitaxial islands by selectively directing a beam of ions of second conductivity type through the nitride layer (28) and epitaxial oxide buffer layer into the epitaxial layer at collector sink region surface locations; retaining the nitride layer and epitaxial oxide buffer layer in place as a barrier to environmental contaminants; implanting base regions (40) in the epitaxial islands by selectively directing a beam of ions of first conductivity type through the nitride layer (28) and epitaxial oxide buffer layer (16) into the epitaxial layer at base region surface locations before implanting emitter regions; retaining the nitride layer and epitaxial oxide buffer layer in place as a barrier to environmental contaminants; forming a self-aligned transistor mask pattern over the nitride layer (28) for defining the surface locations of collector sink, base and emitter regions in self-alignment relative to each other on the epitaxial islands through openings in the self-aligned transistor mask pattern; etching the underlying nitride layer (28) through the openings in the self-aligned transistor mask pattern and removing the nitride layer at the surface locations of the collector sink, base and emitter regions while retaining the epitaxial oxide buffer layer (16) in place as a barrier to environmental contaminants; removing the self-aligned transistor mask pattern, retaining the unetched remainder of the nitride layer in place, and retaining the epitaxial oxide buffer layer in place at the surface locations where the nitride layer was removed by etching; implanting emitter regions (50) in base regions (40) previously implanted in the epitaxial islands by selectively directing a beam of ions of second conductivity type through the epitaxial oxide buffer layer into the epitaxial layer; simultaneously annealing the implanted collector sink, base and emitter regions thereby providing a substantially isoplanar integrated circuit structure of active and passive elements in the epitaxial islands separated by said isolation oxide regions.

Claim 2

A method for fabricating a bipolar substantially isoplanar integrated circuit structure on a substrate of semiconductor material of a first conductivity type, said substrate being processed by depositing an epitaxial layer (15) of semiconductor material over the substrate thereby forming an isolation junction extending laterally through the structure between the epitaxial layer and sustrate, forming a thin epitaxial oxide buffer layer (16) over the epitaxial layer, subdividing said structure into a plurality of epitaxial islands (25) in which active and passive elements are fabricated, and isolating said epitaxial islands relative to each other by forming annular shaped isolation oxide regions (22) of oxidized semiconductor material extending through the epitaxial layer to the isolation junction, characterized in that the method comprises : depositing a uniform nitride layer (28) over the structure thereby passivating the structure and protecting the isolation oxide regions, epitaxial oxide buffer layer and epitaxial layer from contaminants; implanting collector sink regions (30) in the epitaxial islands by selectively directing a beam of ions of second conductivity type through the nitride layer (28) and epitaxial oxide buffer layer into the epitaxial layer at collector sink region surface locations; retaining the nitride layer and epitaxial oxide buffer layer in place as a barrier to environmental contaminants; implanting base regions (40) in the epitaxial islands by selectively directing a beam of ions of first conductivity type through the nitride layer (28) and epitaxial oxide buffer layer (16) into the epitaxial layer at base region surface locations before implanting emitter regions; retaining the nitride layer and epitaxial oxide buffer layer in place as a barrier to environmental contaminants; forming a self-aligned transistor mask pattern over the nitride layer (28) for defining the surface locations of collector sink, base and emitter regions in self-alignment relative to each other on the epitaxial islands through openings in the self-aligned transistor mask pattern; etching the underlying nitride layer (28) through the openings in the self-aligned transistor mask pattern and removing the nitride layer at the surface locations of the collector sink, base and emitter regions while retaining the epitaxial oxide buffer layer (16) in place as a barrier to environmental contaminants; removing the self-aligned transistor mask pattern, retaining the unetched remainder of the nitride layer in place, and retaining the epitaxial oxide buffer layer in place at the surface locations where the nitride layer was removed by etching; implanting emitter regions (50) in base regions (40) previously implanted in the epitaxial islands by selectively directing a beam of ions of second conductivity type through the epitaxial oxide buffer layer into the epitaxial layer; simultaneously annealing the implanted collector sink, base and emitter regions thereby providing a substantially isoplanar integrated circuit structure of active and passive elements in the epitaxial islands separated by said isolation oxide regions.

Claim 5

The method of any one of claims 1 to 3 characterized by comprising the step of directing a beam of ions of second conductivity type into the collector sink regions (30) a second time while implanting emitter regions (50) thereby overdoping the surface locations (31) of the collector sink regions to reduce surface contact resistance.

Claim 6

The method of any one of claims 1 to 4 characterized by comprising the preliminary step of forming the isolation oxide regions (22) in the preferred temperature range of 1050°C to 1100°C thereby sustantially reducing the viscosity of the oxidized semiconductor material and eliminating the fracturing of epitaxial islands.

Claim 7

The method any one of clains 1 to 5 characterized by comprising the step of field implanting gettering ions of phosphorus in the isolation oxide regions (22).

Claim 8

The method any one of clains 1 to 5 characterized by comprising the step of field implanting gettering ions of phosphorus in the isolation oxide regions (22).

Claim 9

The method of any one of claims 1 to 6 characterized in that each said implanting step of collector sink regions (30) and of base regions (40) comprises : forming an implant mask (35,36) of resist material in a pattern over the nitride layer (28) for defining selected regions in the epitaxial islands (25) through openings formed in the implant mask; implanting selected ions through said implant mask openings and removing the implant mask.

Claim 12

The method of any one of claims 1 to 9 characterized in that said step of etching the underlying nitride layer (28) comprises wet etching.

Claim 13

The method of any one of claims 1 to 9 characterized in that said step of etching the underlying nitride layer (28) comprises plasma etching.