← Back to Patent Explorer
EP0133709A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Photodetector integrated circuit

Assignee: ITT Inc
•
Filing: 1984-08-11
•
Granted: —
•
Expires: 2004-08-11
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An integrated circuit incorporating a PIN diode connected to the gate of an FET, wherein the semiconductive layers used to construct the diode are also the layers used to construct the FET, and provide a relatively low capacitance per unit area for the diode compared with that ot the gate of the FET.

Inventors

  • 👤 John Christopher Greenwood

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 22:23
CPC Classifications
H; H10; H10F; H10F99/00; H10F39/00; H10F39/10; H10F39/103; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/05; H10F30/00; H10F30/20; H10F30/21; H10F30/22; H10F30/223; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/646

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 71 words
A photodetector integrated circuit incorporating a PIN photodiode (PIN-diode) connnected to the gate of field effect transistor (FET), wherein the semiconductive layers from which the diode is constructed are also the layers from which the FET is constructed, and their construction is such as to provide the PIN-diode with a capacitance per unit area that is small compared with the gate capacitance of the FET per unit area of that gate.
Claim 2
Dependent Claim 71 words
A photodetector integrated circuit incorporating a PIN photodiode (PIN-diode) connnected to the gate of field effect transistor (FET), wherein the semiconductive layers from which the diode is constructed are also the layers from which the FET is constructed, and their construction is such as to provide the PIN-diode with a capacitance per unit area that is small compared with the gate capacitance of the FET per unit area of that gate.
Claim 3
Dependent Claim 49 words
An integrated circuit as claimed in claim 1, wherein the semiconductive layers are grown upon an indium phosphide substrate and include an n-type layer that-forms the channel layer (4) of the FET and covers an n -type or semi-insulating buffer layer (3) that is thicker than the channel layer.
Claim 4
Dependent Claim 40 words
An integrated circuit as claimed in claim 2, wherein the buffer layer (3) is approximately 1 micron thick and is made of material having a band gap that is less than that of any layer with which it is covered.
Claim 5
Dependent Claim 54 words
An integrated circuit as claimed in claim 2 or 3, wherein the buffer layer (3) is approximately 1 micron thick and is made of material having a band gap that is less than that of the substrate of the integrated circuit and of any layer intermediate the buffer layer (3) and the substrate (1).
Claim 6
Dependent Claim 15 words
An integrated circuit as claimed in any preceding claim, wherein the FET is a HEMT.
Claim 7
Dependent Claim 38 words
An integrated circuit as claimed in claim 1, 2, 3 or 4, wherein the FET is of a type in which source drain current conduction occurs in the channel layer (4) rather than in the buffer layer (3).
Claim 8
Dependent Claim 15 words
An integrated circuit as claimed in any preceding claim, wherein the FET is a JFET.
Claim 9
Dependent Claim 75 words
An integrated circuit as claimed in claim 6, wherein the p-n junction is bounded on its upper side by a stack of three layers (4,5,6) whose compositions lie in the range from indium phosphide through gallium indium arsenide phosphide to gallium indium arsenide, and are such that the topmost has a band gap in the region of 1.2 eV, the bottommost a substantially higher band gap, and the middle layer a substantially lower band gap.
Claim 10
Dependent Claim 20 words
An integrated circuit as claimed in any preceding claim, which integrated circuit includes a bias resistor for the PIN diode.
Claim 11
Dependent Claim 43 words
An integrated circuit as claimed in claim 9, which integrated circuit includes a second FET whose gate is connected to the drain of the first FET and which integrated circuit also includes a load resistor connected to the drain of the first FET.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag