EP0133667A2
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EP
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High coupling ratio dense electrically erasable programmable read-only memory
Assignee: American Microsystems Holding Corp
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Filing: 1984-07-25
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Granted: —
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Expires: 2004-07-25
Abstract
Abstract A unique EEPROM cell is fabricated which is significantly different in construction than prior art EEPROMS, but which is capable of being fabricated using well known semiconductor processing techniques. In one embodiment, the EEPROM cell (10) includes not only a source region (18-2), a channel region (18-4), and a drain region 18-3) located within a semiconductor substrate (11), but also a separate and distinct programming region (18-1). A tunnelling dielectric (20), an oxide, ratherthan being formed overthe drain region (18-3), is located over the tunnelling region (20), and a floating gate (21) extends not only over the channel region (18-4) and the drain region (18-3), but over the source region (18-2) and the tunnelling region (20) as well. The EEPROM memory cell (10) constructed in this manner allows greater efficiency than prior art EEPROMS and greater control over the capacitances of the cell, which determines cell efficiency.
Inventors
- 👤 Ron Maltiel
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 17:01
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
209 words
An electrically erasable programmable read only memory comprising a semiconductor substrate (11) of a first conductivity type, a source region (18-2) being of a second conductivity type opposite said first conductivity type, a drain region (18-3) formed within said substrate (-11), said drain region (18-3) being of said second conductivity type and spaced apart from said source region (18-2), a channel region (18-4) located within said substrate (11) between said source region (18-2) and said drain region (18-3), said electrically erasable programmable read-only memory (10) characterized by: a programming region (18-1) formed in said substrate (11), said programming region (18-1) being located apart from said source region (18-2) and said drain region (18-3); a layer of gate dielectric (19) formed on the surface of said substrate (11) above said source region (18-2), said drain region (18-3), and said channel region (18-4); a tunnelling dielectric (20) formed on the surface of said substrate (11) above at least a portion of said programming region (18-1), and a floating gate region (21) formed above at least said channel region (18-4) and a portion of said programming region (18-1) and separated from said channel region (18-4) by said gate dielectric (19) and separated from said programming region (18-1) by said tunnelling dielectric (20).
Claim 2
Dependent Claim
209 words
An electrically erasable programmable read only memory comprising a semiconductor substrate (11) of a first conductivity type, a source region (18-2) being of a second conductivity type opposite said first conductivity type, a drain region (18-3) formed within said substrate (-11), said drain region (18-3) being of said second conductivity type and spaced apart from said source region (18-2), a channel region (18-4) located within said substrate (11) between said source region (18-2) and said drain region (18-3), said electrically erasable programmable read-only memory (10) characterized by: a programming region (18-1) formed in said substrate (11), said programming region (18-1) being located apart from said source region (18-2) and said drain region (18-3); a layer of gate dielectric (19) formed on the surface of said substrate (11) above said source region (18-2), said drain region (18-3), and said channel region (18-4); a tunnelling dielectric (20) formed on the surface of said substrate (11) above at least a portion of said programming region (18-1), and a floating gate region (21) formed above at least said channel region (18-4) and a portion of said programming region (18-1) and separated from said channel region (18-4) by said gate dielectric (19) and separated from said programming region (18-1) by said tunnelling dielectric (20).
Claim 3
Dependent Claim
47 words
The electrically erasable programmable read only memory according to claim 1 further characterized by: a floating gate dielectric layer (22) formed above said floating gate (21); and a control gate (23) formed above said floating gate (21) and insulated therefrom by said floating gate dielectric layer (22).
Claim 4
Dependent Claim
25 words
The electrically erasable programmable read only memory according to claim 1 or 2, characterized in that said programming region (18-1) is of said.second conductivity type.
Claim 5
Dependent Claim
37 words
The electrically erasable programmable read only memory according to any one of claims 1 - 3, characterized in that said programming region (18-1) is separated from said source region (18-2) by a layer of field oxide (16).
Claim 6
Dependent Claim
26 words
The electrically erasable programmable read only memory according to any one of claims 2 - 4, characterized in that said floating gate (21) comprises polycrystalline silicon.
Claim 7
Dependent Claim
49 words
The electrically erasable programmable read only memory according to any one of claims 2 - 5, characterized in that said control gate (23) comprises material selected from the group of materials consisting of polycrystalline silicon, doped polycrystalline silicon, aluminum, alloys of aluminum, refractory metals, and alloys of refractory metals.
Claim 8
Dependent Claim
28 words
The electrically erasable programmable read only memory according to any one of claims 1 - 6 characterized in that said gate dielectric (19) comprises an oxide of silicon.
Claim 9
Dependent Claim
31 words
The electrically erasable programmable read only memory according to claim 7 characterized in that said gate dielectric layer (19) has a thickness within the 0 range of approximately less than 1000A.
Claim 10
Dependent Claim
28 words
The electrically erasable programmable read only memory according to any one of claims 1 - 8, characterized in that said tunnelling dielectric (20) comprises an oxide of silicon.
Claim 11
Dependent Claim
30 words
The electrically erasable programmable read only memory according to claim 9, characterized in that said tunnelling dielectric (20) has a thickness within the 0 range of approximately less than 250A.
Claim 12
Dependent Claim
37 words
The electrically erasable programmable read only memory according to any one of claims 1 - 8, characterized in that said tunnelling dielectric (20) comprises a first layer of silicon dioxide and a second layer of silicon nitride.
Claim 13
Dependent Claim
30 words
The electrically erasable programmable read only memory according to any one of claims 2 - 11, characterized in that said control gate (23) ist connected to said drain region (18-3).
Claim 14
Independent Claim
113 words
A method for programming an electrically erasable programmable read only memory having a source, a channel, a drain, and a programming region formed within a semiconductor substrate, a floating gate separated from said source, channel, and drain region by a gate oxide, and separated from said programming region by a tunnelling dielectric, and a control gate, said method characterized by the steps of: connecting said programming region to said first selected voltage; connecting said control gate to a second selected voltage; connecting said source to said second selected voltage; and connecting said drain to said second selected voltage, whereby electrons tunnel between said programming region and said floating gate through said tunnelling dielectric.
Claim 15
Independent Claim
113 words
A method for programming an electrically erasable programmable read only memory having a source, a channel, a drain, and a programming region formed within a semiconductor substrate, a floating gate separated from said source, channel, and drain region by a gate oxide, and separated from said programming region by a tunnelling dielectric, and a control gate, said method characterized by the steps of: connecting said programming region to said first selected voltage; connecting said control gate to a second selected voltage; connecting said source to said second selected voltage; and connecting said drain to said second selected voltage, whereby electrons tunnel between said programming region and said floating gate through said tunnelling dielectric.
Claim 16
Independent Claim
141 words
A method for forming an electrically erasable programmable read only memory in a semiconductor substrate comprising the steps of forming on the surface of said substrate thick field oxide regions in those areas where active regions are not to be formed, forming in said substrate a first region of a second conductivity type opposite said first conductivity type which is to serve as a drain region, and a second region of said second conductivity type to serve as a source region, wherein the portion of said substrate located between said source and said drain region will serve as a channel region, said method characterized by the steps of: forming a tunnelling region within said substrate and separated from said source, drain, and channel regions; and forming a floating gate electrode above and insulated from said drain, channel, source, and tunnelling regions.
Claim 17
Independent Claim
141 words
A method for forming an electrically erasable programmable read only memory in a semiconductor substrate comprising the steps of forming on the surface of said substrate thick field oxide regions in those areas where active regions are not to be formed, forming in said substrate a first region of a second conductivity type opposite said first conductivity type which is to serve as a drain region, and a second region of said second conductivity type to serve as a source region, wherein the portion of said substrate located between said source and said drain region will serve as a channel region, said method characterized by the steps of: forming a tunnelling region within said substrate and separated from said source, drain, and channel regions; and forming a floating gate electrode above and insulated from said drain, channel, source, and tunnelling regions.
Claim 18
Dependent Claim
25 words
The method according to claim 14, further characterized by the step .of forming a control gate electrode above and electrically insulated from said floating gate.
Claim 19
Dependent Claim
20 words
The method according to claim 14 or 15, characterized in that said tunnelling region is of said second conductivity type.
Claim 20
Dependent Claim
26 words
The method according to claim 14 or 15, characterized in that a thin tunnelling dielectric is formed between said tunnelling region in said floating gate electrode.
Claim 21
Independent Claim
29 words
The method according to any one of claims 14 - 17, characterized in that said tunnelling region is separated from said source region by a thick field oxide region.
Claim 22
Independent Claim
24 words
The method according to any one of claims 14 - 18, characterized in that said control gate is electrically connected to said drain region.
References Cited (Backward Citations)
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