Patent US3999752A successfully refreshed from Google Patents.
EP0133359A2
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EP
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Chipset synchronization arrangement
Assignee: AT&T Inc
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Filing: 1984-07-27
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Granted: —
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Expires: 2004-07-27
Abstract
Abstract Each chip (11, 12) of a microprocessor chipset is synchronized by an associated controller (400) which adjusts a control signal (202) for controlling the delay of a variable delay circuit during each operating cycle. The controller tailors the control signal for each chip by an op-amp (507) which compares the output of an internal clock in each chip with a reference system voltage (508).
Inventors
- 👤 Masakazu Shoji
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 13:46
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
161 words
A circuit arrangement for synchronizing clock pulses in a chipset, said chipset comprising at least first and second integrated circuit chips (11, 12) in each of which a plurality of components (16, 17) is defined, CHARACTERIZED IN THAT each of said chips (11, 12) incldes an arrangement of adjustable delay circuits (16, 17) for providing internal clock pulses (on 202) in response to a system clock signal (on 13) and including control means (400) for adjusting the delay of said internal clock pulses in response to said system clock signal, said circuit arrangement comprising at least first control signal gnerating circuits (500-507) for generating individual control signals (on 301) for said first and second chips respectively, each of said control signal generating circuits being responsive to said system clock signal and one of said internal clock pulses from an associated one of said first and second chips for adjusting the delay of said internal clock pulses during a next clock cycle.
Claim 2
Dependent Claim
161 words
A circuit arrangement for synchronizing clock pulses in a chipset, said chipset comprising at least first and second integrated circuit chips (11, 12) in each of which a plurality of components (16, 17) is defined, CHARACTERIZED IN THAT each of said chips (11, 12) incldes an arrangement of adjustable delay circuits (16, 17) for providing internal clock pulses (on 202) in response to a system clock signal (on 13) and including control means (400) for adjusting the delay of said internal clock pulses in response to said system clock signal, said circuit arrangement comprising at least first control signal gnerating circuits (500-507) for generating individual control signals (on 301) for said first and second chips respectively, each of said control signal generating circuits being responsive to said system clock signal and one of said internal clock pulses from an associated one of said first and second chips for adjusting the delay of said internal clock pulses during a next clock cycle.
Claim 3
Dependent Claim
58 words
A circuit arrangement in accordance with claim 1 wherein each of said control signal generating circuits includes an op-amp (507) having first and second inputs and an output, first means (500-504) for applying said internal clock pulse from an associated chip to said first input and second means for applying a reference voltage (508) to said second input.
Claim 4
Dependent Claim
23 words
A circuit arrangement in accordance with claim 2 wherein said first means comprises an AND circuit (500, 501) and a filter (503, 504).
Claim 5
Dependent Claim
26 words
A circuit arrangement in accordance with claim 3 wherein a plurality of said control signal generating circuits is defined in a single integrated circuit controller chip.
Claim 6
Dependent Claim
15 words
A circuit arrangement in accordance with claim 4 including a plurality of integrated circuit chips.
Claim 7
Dependent Claim
60 words
A circuit arrangement in accordance with claim 1 wherein said arrangement of adjustable delay circuits includes means (FIG. 6) for adjusting the leading and trailing edges of clock-in pulses applied thereto in response to first and second internal control signals, (C 1 , C 2 ), respectively, and means (170, 171) for providing said first and second internal control signals.
Claim 8
Dependent Claim
64 words
A circuit arrangement in accordance with claim 1 wherein said first control signal generating circuits comprise means (FIG. 8) associated with each of said chips for adjusting leading and trailing edges of a clock-in pulse applied to an associated one of said chips responsive to a system clock signal and one of said internal clock pulses (on 202) applied thereto from said associated chip.
References Cited (Backward Citations)
No citation records indexed.
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