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EP0132832A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Circuit for detecting picture motion in interlaced television signal

Assignee: Hitachi Ltd
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Filing: 1984-07-24
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Granted: —
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Expires: 2004-07-24
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Abstract

Abstract Disclosed is a motion detecting circuit for detecting the motion of an object in an interlaced television signal, in which at least three field memories (58, 59, 60) are connected in cascade, and an inter-field difference signal and an inter-frame difference signal are detected from input and output signals of these field memories (58, 59, 60), whereby a signal indicating the existence of movement of the object is produced when movement is detected in the inter-field difference signal or the inter-frame difference signal.

Inventors

  • 👤 Masahiko Achiha

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-28 12:28
CPC Classifications
H; H04; H04N; H04N9/00; H04N5/00; H04N5/14; H04N5/144; G; G06; G06T; G06T7/00; G06T7/20; G06T7/254; H04N19/00; H04N19/50; H04N19/503

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 120 words
A motion detecting circuit for detecting the motion of an object in an interlaced television signal comprising: an input terminal (41, 51) to which the interlaced television signal is applied; a plurality of memories (21 to 25, 53, 54, 58 to 60) connected in series to said input terminal, the sum of capacities of said plurality of memories (21 to 25, 53, 54, 58 to 60) corresponding to at least three fields; a first circuit (33, 35, 37) for calculating at least two inter-frame difference signals of successive fields from said plurality of memories; and a second circuit (39, 40, 44, 45) for calculating the motion of said object by utilizing the output of said first circuit (33, 35, 37).
Claim 2
Dependent Claim 120 words
A motion detecting circuit for detecting the motion of an object in an interlaced television signal comprising: an input terminal (41, 51) to which the interlaced television signal is applied; a plurality of memories (21 to 25, 53, 54, 58 to 60) connected in series to said input terminal, the sum of capacities of said plurality of memories (21 to 25, 53, 54, 58 to 60) corresponding to at least three fields; a first circuit (33, 35, 37) for calculating at least two inter-frame difference signals of successive fields from said plurality of memories; and a second circuit (39, 40, 44, 45) for calculating the motion of said object by utilizing the output of said first circuit (33, 35, 37).
Claim 3
Dependent Claim 34 words
A motion detecting circuit according to claim 1, wherein said interlaced television signal applied to said input terminal (41, 51) is a luminance signal or a low frequency signal of a color television signal.
Claim 4
Dependent Claim 19 words
A motion detecting circuit according to claim 2, wherein said color television signal is an NTSC color television signal.
Claim 5
Dependent Claim 184 words
A motion detecting circuit according to claim 2, wherein said plurality of memories are a first (21), a second (22), a third (23), a fourth (24), and a fifth (25) memories connected in series in the mentioned order and having 262H, 1H, 262H, 262H, and 1H, said H being a capacity of a scanning line; wherein said first circuit (33, 35, 37) includes a first subtracter (33) for obtaining the difference between an input signal to said first memory (21) and the output of said third memory (23), a second subtracter (35) for obtaining the difference between the respective outputs of said first (21) and fourth (24) memories, a third subtracter (37) for obtaining the difference between the respective outputs of said second (22) and fifth (25) memories, and a plurality of absolute value circuits (34, 36, 38) connected to said respective subtracters (33, 35, 37); and wherein said second circuit (39, 40, 44, 45) produces a signal indicating the existence of picture movement when one of the respective outputs of said plurality of absolute value circuits (34, 36, 38) exceeds a predetermined value.
Claim 6
Dependent Claim 101 words
A motion detecting circuit according to claim 2, further comprising a band pass filter (42) for extracting a high frequency component of said color television signal including a chrominance subcarrier, a third circuit (53 to 67) for obtaining an inter-field difference signal of television signal or absolute values of inter-field difference signal so as to obtain an inter-frame difference signal as to the inter-field difference signal or as to the absolute values of inter-field difference signal, and a fourth circuit (44) for producing motion information of the object on the basis of the respective outputs of said second and third circuits.
Claim 7
Dependent Claim 74 words
A motion detecting circuit according to claim 5, wherein said third circuit includes a fourth subtracter (55, 61) for obtaining the difference between the output of said filter and a signal obtained by delaying said output of said filter (42) by one field, and a fifth subtracter (56) for obtaining the difference between the output of said fourth subtracter and a signal obtained by delaying said output of said fourth subtracter by one frame.
Claim 8
Dependent Claim 97 words
A motion detecting circuit according to claim 5, wherein said third circuit includes a fourth subtracter (55) for obtaining the difference between the output of said filter (42) and a signal obtained by delaying said output of said filter (42) by one field, and a second absolute circuit (57) for obtaining an absolute value of the output of said fourth subtracter (55), and a fifth subtracter (56) for obtaining the difference between the output of said second absolute circuit (57) and a signal obtained by delaying said output of said second absolute circuit (57) by one frame.
Claim 9
Dependent Claim 106 words
A motion detecting circuit according to claim 5, wherein said third circuit includes a series connection of a first, a second, and a third field memories (58, 59, 60), said connection having an input connected to the output of said filter, a sixth subtracter (61) for obtaining the difference between the input and output of said first field memory (58), a seventh subtracter (62) for obtaining the difference between the respective outputs of said second field memory (59) and said sixth subtracter (61), and an adder (63) for obtaining the sum of the respective outputs of said third field memory (60) and said seventh subtracter (62).
Claim 10
Dependent Claim 101 words
A motion detecting circuit according to claim 5, wherein said third circuit includes a series connection of a first, a second, and a third field memories (58, 59, 60), said connection having an input connected to the output of said filter (42), a sixth subtracter (61) for obtaining the difference between the input and output of said first field memory (58), a eighth subtracter (65) for obtaining the difference between the input and output of said third field memory (60), and a ninth subtracter (67) for obtaining the difference between the respective outputs of said sixth and eighth subtracters (61, 65).
Claim 11
Dependent Claim 181 words
A motion detecting circuit according to claim 3, wherein said plurality of memories are a first (21), a second (22), a third (23), a fourth (24), and a fifth (25) memories connected in series in the mentioned order and having 262H, 1H, 262H, 262H, and 1H, said H being a capacity of a scanning line; wherein said first circuit (33, 35, 37) includes a first subtracter (33) for obtaining the difference between an input signal to said first memory (21) and the output of said third memory (23), a second subtracter (35) for obtaining the difference between the respective outputs of said first (21) and fourth (24) memories, a third subtracter (37) for obtaining the difference between the respective outputs of said second (22) and fifth (25) memories, and a plurality of absolute value circuits (34, 36, 38) connected to said respective subtracters; and wherein said second circuit (39, 40, 44, 45) produces a signal indicating the existence of picture movement when one of the respective outputs of said plurality of absolute value circuits (34, 36, 38) exceeds a predetermined value.

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