EP0132158A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method of performing a sequence of related activities in multiple independent digital processors
Assignee: Unisys Corp
•
Filing: 1984-07-19
•
Granted: —
•
Expires: 2004-07-19
Abstract
Abstract A method of performing a sequence of related activities in multiple digital processors includes the steps of: executing a portion of a first activity of the sequence in a first processor and then executing an INTERPROCESSOR CALL instruction to a second activity in a second processor; suspending execution of the first activity in response to the CALL and signaling the second processorthatthe second activity has been called by the first activity; completely executed the second activity in the second processor and then executing an INTERPROCESSOR NEXT instruction to a third activity in a third processor; signaling the third processor in response to the NEXT instruction that the third activity has been called not by the second activity but by the caller of the second activity; and completely executing the third activity in the third processer and, upon completion thereof, signaling the third activity's caller to resume execution of the suspended activity.
Inventors
- 👤 Christopher Jerome Tomlinson
- 👤 Howard Hunt Green
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 18:03
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/54; G06F9/547
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
164 words
A method of performing a task as a sequence of called activities in multiple digital processors some of which are not returned to after the sequence is complete, including the steps of: executing a portion of a first activity of said sequence in a first processor up to an INTERPROCESSOR CALL instruction; suspending execution of the first activity in response to said CALL and signaling a second processor that a second activity has been called by the first activity; completely executing the second activity in the second processor in response to said CALL and further executing an INTERPROCESSOR NEXT instruction to a third activity in a third processor; signaling the third processor in response to said NEXT instruction that said third activity has been called not by said second activity but by the caller of the second activity; and completely executing said third activity in said third processor and, upon completion thereof, signaling said third activity's caller to resume execution of said suspended activity.
Claim 2
Independent Claim
164 words
A method of performing a task as a sequence of called activities in multiple digital processors some of which are not returned to after the sequence is complete, including the steps of: executing a portion of a first activity of said sequence in a first processor up to an INTERPROCESSOR CALL instruction; suspending execution of the first activity in response to said CALL and signaling a second processor that a second activity has been called by the first activity; completely executing the second activity in the second processor in response to said CALL and further executing an INTERPROCESSOR NEXT instruction to a third activity in a third processor; signaling the third processor in response to said NEXT instruction that said third activity has been called not by said second activity but by the caller of the second activity; and completely executing said third activity in said third processor and, upon completion thereof, signaling said third activity's caller to resume execution of said suspended activity.
Claim 3
Dependent Claim
43 words
A method according to Claim 1 and further including the step of signaling said second processor in response to said NEXT instruction to re-execute said second activity for any other callers thereof while said third activity is being executed by said third processor.
Claim 4
Dependent Claim
52 words
A method according to Claim 1 and further including the steps of: providing each activity with a queue containing pointers to the respective callers of that activity; and moving the caller pointer from the queue of the second activity into the queue of the third activity in response to said NEXT instruction.
Claim 5
Dependent Claim
35 words
A method according to Claim 3 and further including the step of limiting access to said queues such that said pointers are loaded and unloaded during multiple cycles by only one processor at a time.
Claim 6
Dependent Claim
25 words
A method according to Claim 1 and further including the step of executing another activity in said first processor while said first activity is suspended.
Claim 7
Dependent Claim
169 words
A data processing system including first, second and third digital processors, for performing a task as a sequence of called activities of which some are not returned to when the sequence is complete, including: means for directing said first processor to execute a portion of a first activity in said sequence up to an INTERPROCESSOR CALL instruction; means for signaling a second processor in response to said CALL instruction that a second activity has been called by said first activity; means for directing said second processor to completely execute said second activity and further execute an INTERPROCESSOR NEXT instruction to a third activity in a third processor; means for signaling said third processor in response to said NEXT instruction that said third activity has been called not by said second activity but by the caller of said first activity; and means for directing said third processor to completely execute said third activity, and upon completion thereof, to signal said third activity's caller to resume execution of said suspended activity.
Claim 8
Dependent Claim
169 words
A data processing system including first, second and third digital processors, for performing a task as a sequence of called activities of which some are not returned to when the sequence is complete, including: means for directing said first processor to execute a portion of a first activity in said sequence up to an INTERPROCESSOR CALL instruction; means for signaling a second processor in response to said CALL instruction that a second activity has been called by said first activity; means for directing said second processor to completely execute said second activity and further execute an INTERPROCESSOR NEXT instruction to a third activity in a third processor; means for signaling said third processor in response to said NEXT instruction that said third activity has been called not by said second activity but by the caller of said first activity; and means for directing said third processor to completely execute said third activity, and upon completion thereof, to signal said third activity's caller to resume execution of said suspended activity.
Claim 9
Dependent Claim
41 words
A system according to Claim 6 and further including means for signaling said second processor to execute said second activity for any other callers thereof while said third activity is'being executed by said third processor in response to said NEXT instruction.
Claim 10
Dependent Claim
51 words
A system according to Claim 6 and further including: a queue means for each activity containing pointers to the respective callers of that activity; and means for moving the caller pointer from the queue of said second activity into the queue of said third activity in response to said NEXT instruction.
Claim 11
Dependent Claim
35 words
A system according to Claim 8 and further including a means for limiting access to said queues such that said pointers are loaded and unloaded during multiple cycles by only one processor at a time.
Claim 12
Dependent Claim
24 words
A system according to Claim 6 and further including means for executing another activity in the first processor while said first activity is suspended.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.