EP0132129A2
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EP
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Address translation buffer
Assignee: Unisys Corp
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Filing: 1984-07-13
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Granted: —
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Expires: 2004-07-13
Abstract
Abstract An apparatus is disclosed that translates virtual memory addresses into physical memory addresses. In particular, this apparatus comprises a plurality of rows of content addressable memory cells, a corresponding plurality of random access memory cells and another corresponding plurality of control circuits. The content addressable memory cells store the virtual memory addresses and the random access memory cells store the physical memory addresses. The control circuits are coupled to both the content addressable and the random access memory cells and are disposed for controlling the operation of the apparatus.
Inventors
- 👤 Burton Lee Levin
- 👤 Andrew Everett Phelps
- 👤 Hanan Potash
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 09:42
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
198 words
An apparatus for translating a selected one of a first group of binary numbers into another binary number selected from a second group of binary numbers, said apparatus comprising: a plurality of rows of content addressable memory cells being disposed for storing said first group of binary numbers and each row being adaptable for providing a match signal when said selected one of said first group of binary nunbers is located; a corresponding plurality of rows of random access memory cells being disposed for storing said second group of binary nunbers and each row being adaptable for accessing the contents thereof in response to said match signal; and, another corresponding plurality of rows of control circuits coupled to both said content addressable memory cells and said random access memory cells and being disposed for rewriting said binary numbers into the first row of memory cells upon access thereof in response to a match signal and shifting down one row all other binary numbers stored in said apparatus above the accessed row, whereby the order of last access of the binary numbers is maintained such that the last row of memory cells contains the least recently used binary numbers.
Claim 2
Independent Claim
198 words
An apparatus for translating a selected one of a first group of binary numbers into another binary number selected from a second group of binary numbers, said apparatus comprising: a plurality of rows of content addressable memory cells being disposed for storing said first group of binary numbers and each row being adaptable for providing a match signal when said selected one of said first group of binary nunbers is located; a corresponding plurality of rows of random access memory cells being disposed for storing said second group of binary nunbers and each row being adaptable for accessing the contents thereof in response to said match signal; and, another corresponding plurality of rows of control circuits coupled to both said content addressable memory cells and said random access memory cells and being disposed for rewriting said binary numbers into the first row of memory cells upon access thereof in response to a match signal and shifting down one row all other binary numbers stored in said apparatus above the accessed row, whereby the order of last access of the binary numbers is maintained such that the last row of memory cells contains the least recently used binary numbers.
Claim 3
Dependent Claim
35 words
An apparatus as in Claim 1 wherein each of said control circuits includes means for generating a shift signal for shifting down one row all binary numbers stored in said apparatus above the accessed row.
Claim 4
Dependent Claim
29 words
An apparatus as in Claim 2 wherein each of said control circuits includes means for inhibiting the generation of said shift signal for all rows below said accessed row.
Claim 5
Dependent Claim
43 words
An apparatus as in Claim 1 wherein each of said control circuits includes means for generating an entry not present signal when a selected binary number is not not stored in any of said plurality of rows of said content addressable memory cells.
Claim 6
Dependent Claim
33 words
An apparatus as in Claim 1 wherein each of said control circuits includes neans for shifting the binary numbers stored in all of said rows of content addressable and random access memory cells.
Claim 7
Dependent Claim
28 words
An apparatus as in Claim 1 wherein each of said rows of random access memory cells includes means for representing a valid entry of a binary number therein.
Claim 8
Dependent Claim
34 words
An apparatus as in Claim 1 further including a control state machine being disposed for providing control signals to said apparatus in response to status signals from said apparatus and from external control signals.
Claim 9
Dependent Claim
16 words
An apparatus as in Claim 1 wherein said control state machine includes a programmable control matrix.
Claim 10
Dependent Claim
28 words
An apparatus as in Claim 1 wherein each of said rows of random access memory cells includes means for representing a locked entry of a binary number therein.
Claim 11
Independent Claim
196 words
An apparatus for translating a selected one of a group of virtual addresses into a physical address selected from a group of physical addresses corresponding to each of said virtual addresses, said apparatus comprising: a plurality of rows of content addressable memory cells being disposed for storing said group of virtual addresses and each row being adaptable for providing a match signal when said selected one of said group of virtual addresses is located; a corresponding plurality of rows of random access memory cells being disposed for storing said group of physical addresses and each row being adaptable for accessing the contents thereof in response to said match signal; and, another corresponding plurality of rows of control circuits coupled to both said content addressable memory cells and said random access memory cells and being disposed for rewriting said addresses into the first row of memory cells upon access thereof in response to a match signal and shifting down one row all other addresses stored in said apparatus above the accessed row, whereby the order of last access of the addresses is maintained such that the last row of memory cells contains the least recently used address.
Claim 12
Independent Claim
196 words
An apparatus for translating a selected one of a group of virtual addresses into a physical address selected from a group of physical addresses corresponding to each of said virtual addresses, said apparatus comprising: a plurality of rows of content addressable memory cells being disposed for storing said group of virtual addresses and each row being adaptable for providing a match signal when said selected one of said group of virtual addresses is located; a corresponding plurality of rows of random access memory cells being disposed for storing said group of physical addresses and each row being adaptable for accessing the contents thereof in response to said match signal; and, another corresponding plurality of rows of control circuits coupled to both said content addressable memory cells and said random access memory cells and being disposed for rewriting said addresses into the first row of memory cells upon access thereof in response to a match signal and shifting down one row all other addresses stored in said apparatus above the accessed row, whereby the order of last access of the addresses is maintained such that the last row of memory cells contains the least recently used address.
Claim 13
Dependent Claim
39 words
ll. An apparatus as in Claim 10 wherein each of said control circuits includes means for generating a shift signal for shifting down one row all virtual and corresponding physical addresses stored in said apparatus above the accessed row.
Claim 14
Dependent Claim
29 words
An apparatus as in Claim 11 wherein each of said control circuits includes means for inhibiting the generation of said shift signal for all rows below said accessed row.
Claim 15
Dependent Claim
42 words
An apparatus as in Claim 10 wherein each of said control circuits includes means for generating an entry not present signal when a selected virtual address is not stored in any of said plurality of rows of said content addressable memory cells.
Claim 16
Dependent Claim
32 words
An apparatus as in Claim 10 wherein each of said control circuits includes means for shifting the addresses stored in all of said rows of content addressable and random access memory cells.
Claim 17
Dependent Claim
28 words
An apparatus as in Claim 10 wherein each of said rows of random access memory cells includes means for representing a valid entry of a binary number therein.
Claim 18
Dependent Claim
28 words
An apparatus as in Claim 10 wherein each of said rows of random access memory cells includes means for representing a locked entry of a binary number therein.
Claim 19
Independent Claim
222 words
An apparatus for translating a selected one of a group of virtual addresses into a physical address selected from a group of physical addresses corresponding to each of said virtual addresses, said apparatus comprising: a plurality of rows of content addressable memory cells being disposed for storing said group of virtual addresses and each row being adaptable for providing a match signal when said selected one of said group of virtual addresses is located; a corresponding plurality of rows of random access memory cells being disposed for storing said group of physical addresses and each row being adaptable for accessing the contents thereof in response to said match signal; another corresponding plurality of rows of control circuits coupled to both said content addressable memory cells and said random access memory cells and being disposed for rewriting said addresses into the first row of memory cells upon access thereof in response to a match signal and shifting down one row all other addresses stored in said apparatus above the accessed row, whereby the order of last access of the addresses is maintained such that the last row of memory cells contains the least recently used address; and, a control state machine being disposed for providing control signals to said apparatus in response to status signals from said apparatus and from external control signals.
Claim 20
Independent Claim
222 words
An apparatus for translating a selected one of a group of virtual addresses into a physical address selected from a group of physical addresses corresponding to each of said virtual addresses, said apparatus comprising: a plurality of rows of content addressable memory cells being disposed for storing said group of virtual addresses and each row being adaptable for providing a match signal when said selected one of said group of virtual addresses is located; a corresponding plurality of rows of random access memory cells being disposed for storing said group of physical addresses and each row being adaptable for accessing the contents thereof in response to said match signal; another corresponding plurality of rows of control circuits coupled to both said content addressable memory cells and said random access memory cells and being disposed for rewriting said addresses into the first row of memory cells upon access thereof in response to a match signal and shifting down one row all other addresses stored in said apparatus above the accessed row, whereby the order of last access of the addresses is maintained such that the last row of memory cells contains the least recently used address; and, a control state machine being disposed for providing control signals to said apparatus in response to status signals from said apparatus and from external control signals.
Claim 21
Dependent Claim
38 words
An apparatus as in Claim 17 wherein each of said control circuits includes means for generating a shift signal for shifting down one row all virtual and corresponding physical addresses stored in said apparatus above the accessed row.
Claim 22
Dependent Claim
29 words
An apparatus as in Claim 17 wherein each of said control circuits includes means for inhibiting the generation of said shift signal for all rows below said accessed row.
Claim 23
Dependent Claim
42 words
An apparatus as in Claim 17 wherein each of said control circuits includes means for generating an entry not present signal when a selected virtual address is not stored in any of said plurality of rows of said content addressable nenory cells.
References Cited (Backward Citations)
No citation records indexed.
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