EP0131277A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Computer hierarchy control
Assignee: Bull HN Information Systems Inc
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Filing: 1984-07-06
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Granted: —
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Expires: 2004-07-06
Abstract
Abstract A multiple processor computer system features a store-into cache arrangement wherein each processor unit of the system has its own unique cache memory unit. Data operated upon by any one of the processor units is stored in the cache memory associated with that processor unit. When a thus modified block of data is required by another one of the processor units, the requested data is transferred directly to the requesting processor unit without having to first transfer the data to a shared main memory. Provision is also made for transferring data, under prescribed conditions from a cache to the main memory, but not as a precondition for transfer to a requesting processor.
Inventors
- 👤 Lane K. Hooker
- 👤 Thomas H. Howell
- 👤 Charles W. Ferrell
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 00:13
CPC Classifications
G; G06; G06F; G06F9/00; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/084
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
199 words
Claim 1. A data processing system comprising: a plurality of data processing units; each such processing unit including a cache memory unit for storing data directly available for the use of the associated processing unit; a main memory unity a central interface unit coupled to interface between individual ones of said plurality of processor units and between said processor units and said main memory unit; each processing unit having access through said central interface unit to extract selected blocks of data from said main memory for storage in the associated cache memory unit, said extracted blocks of data, when modified by said processing units being returned for storage to the cache memory unit of the individual modifying processing unit wherein the latest modification of any modified block of data resides only in the cache unit of the modifying processing unit; and said central interface unit including means responsive to request signals from any one of said plurality of processing units to effect a transfer of a modified block of data from the cache memory unit of another of said plurality of processing units directly to the cache memory unit of the requesting processing unit, bypassing said main memory unit.
Claim 2
Dependent Claim
34 words
Claim 2- A data processing system as set forth in Claim 1 wherein each of said processor units includes means to tag such blocks of data aa resides exclusive in its associated cache unit.
Claim 3
Dependent Claim
47 words
Claim 3. A data processing system as set forth in Claim 2 wherein each of said processing units includes means to reset said tag in its own cache for any such block of data subsequent to the transfer of that block of data to another memory unit.
Claim 4
Dependent Claim
26 words
Claim 4. A data processing system as set forth in Claim 3 wherein said another memory unit includes the cache memory unit of another processing unit.
Claim 5
Dependent Claim
22 words
Claim 5. A data processing system as set forth in Claim 3 wherein said another memory unit includes said main memory unit.
Claim 6
Dependent Claim
89 words
Claim 6. A data processing system as set forth in Claim 2 wherein said central interface unit includes means responsive to request signals from any of said processing units to issue a search request to search the memory units of all of the associated processing units; each of said processing units including means responsive to said search request to identify whether or not such processing unit has stored within its memory unit a tagged version of the requested block of data and to provide an identifying signal indicative thereof.
Claim 7
Dependent Claim
86 words
Claim 7, A data processing system as set forth in Claim 6 wherein said processing units include means for transmitting said identifying signals to said central interface unit; said central interface unit including means responsive to said identifying signals to determine which, if any, of said processing units includes a tagged version of the requested block of data and to initiate the transfer of such a tagged version of said block of data from its resident location to the memory unit of the requesting processing unit.
Claim 8
Dependent Claim
249 words
Claim 8. A data processing system comprising: a plurality of data processing units; each such processing unit including a cache memory unit for storing data directly available for the use of the associated processing unit, each cache memory unit including a data array and a directory array, said directory array comprising a directory of data stored in said data array; each said processing unit further including a ports unit, each ports unit including a ports command register, a duplicate cache directory and a ports swap directory, said duplicate cache directory being a duplicate of said directory array and also including a directory of the data stored in the associated data array; a main memory unit; a central intrface unit.coupled to interface between individual ones of said plurality of processing units and between said processing units and said main memory unit, said central intrface unit including means coupled to receive command signals related to a requested block of data from each of said command registers of said plurality of processing units, and means responsive to said command signals to initiate a search request signal to determine if said requested block of data resides in a memory unit of any of said processing units, and said central interface unit including further means responsive to an afirmative response from one of said processor units to said search request signal to effect a transfer of said requested block of data from its resident location to the memory unit of the requesting processing unit.
Claim 9
Dependent Claim
101 words
Claim 9. A data processing system as set forth in Claim 8 S wherein aaid means responsive to said afirmative response includes a swap buffer associated, respectively, with each of said processing units, for the temporary storage of blocks of data in process of being transferred from one memory unit to another, said swap directory in each processing unit comprising a directory of blocks of data stored in the associated swap buffer, said search request signal effecting an interrogation of such said swap directory and said duplicate cache directory to effect said determination of residency of said requested block of data.
Claim 10
Dependent Claim
148 words
Claim 10. A data processing system as set forth in Claim 9 wherein said means responsive to said affirmative response further includes multiplexing means coupled to said swap buffers, each said swap buffer having an input coupled to receive a block of data from the cache memory unit of associated one of said processing units, and a multiplexing means included in said central interface unit and having input connections from each of said swap buffers and having output means selectively coupled to an input, respectively of said cache memory unit of each of said processing units, said central interface unit being operative in response to said affirmative response to effect the transfer of a block of data from the cache memory unit of one of said processing units, through the associated swap buffer and said multiplexing means directly to the cache memory unit of the requesting processing unit.
References Cited (Backward Citations)
No citation records indexed.
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