EP0130467A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Efficient trace method adaptable to multiprocessors
Assignee: International Business Machines Corp
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Filing: 1984-06-20
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Granted: —
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Expires: 2004-06-20
Abstract
Abstract The method provides a separate trace table (TT) for each CPU in an MP (multiprocessor) to avoid inter-CPU interference in making trace table entries (16) for explicit and implicit tracing instructions enabled by flag bits (E, A, B) in a control register (CR). Explicit tracing entries are made for an enabled explicit tracing (TR) instruction (11). Implicit tracing entries are made for predetermined instructions (when enabled for tracing) which do not have tracing as their primary purpose. A storage operand (12) of the trace instruction (11) contains a disablement field (T) and optionally may contain an enablement-controlling class field (4...7) to improve the integrity of traceable programs. A time stamp and a range of general register (R1...R3) contents is provided in each trace table entry for a tracing instruction. The time stamp enables all trace tables in an MP system to be later merged into a single trace table whenever required.
Inventors
- 👤 Peter H. Gum
- 👤 Ronald M. Smith
- 👤 Arthur L. Levin
- 👤 John H. Wilson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 16:08
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636
Claims Analysis
Total Claims: 163
Claim 1
Independent Claim
12 words
No interference among the CPUs doing tracing to significantly improve MP performance.
Claim 2
Dependent Claim
12 words
No interference among the CPUs doing tracing to significantly improve MP performance.
Claim 3
Dependent Claim
28 words
No tracing interruption to an instruction stream being traced (as long as there is no page boundary crossing) to significantly improve the performance of any CPU doing tracing.
Claim 4
Dependent Claim
28 words
No tracing interruption to an instruction stream being traced (as long as there is no page boundary crossing) to significantly improve the performance of any CPU doing tracing.
Claim 5
Dependent Claim
28 words
A general-purpose trace instruction that supports explicit tracing of a general type by being able to capture the contents of any number of general registers in the CPU.
Claim 6
Dependent Claim
28 words
A general-purpose trace instruction that supports explicit tracing of a general type by being able to capture the contents of any number of general registers in the CPU.
Claim 7
Dependent Claim
20 words
Each CPU having control over implicit tracing by selected branching and address space instructions and explicit tracing by trace instructions.
Claim 8
Dependent Claim
20 words
Each CPU having control over implicit tracing by selected branching and address space instructions and explicit tracing by trace instructions.
Claim 9
Dependent Claim
20 words
Variable-length entries in a trace table to improve the content quality of some trace entries and efficiently use storage space.
Claim 10
Dependent Claim
20 words
Variable-length entries in a trace table to improve the content quality of some trace entries and efficiently use storage space.
Claim 11
Dependent Claim
28 words
Console control over the enablement/disablement of predetermined classes of explicit tracing instructions (which may be in different programs) without needing to modify any program or any operand data.
Claim 12
Dependent Claim
28 words
Console control over the enablement/disablement of predetermined classes of explicit tracing instructions (which may be in different programs) without needing to modify any program or any operand data.
Claim 13
Dependent Claim
22 words
Individual disablement control over each explicit trace instruction in any program by modifying operand data, but without needing to modify any program.
Claim 14
Dependent Claim
22 words
Individual disablement control over each explicit trace instruction in any program by modifying operand data, but without needing to modify any program.
Claim 15
Dependent Claim
130 words
Significantly reduced overhead for page-end boundary checking needed for making entries in any CPU trace table. The invention, as claimed, supports a separate trace table for each CPU in a MP to avoid inter-CPU interference in making trace table entries. Also, the invention provides a time stamp in each explicit trace table entry to enable all trace tables in a MP system to be later merged into a single trace table whenever required. Inter-CPU interference is avoided by providing each CPU with its own trace table and its own interface to its trace table. That is, no other CPU can use a trace table interface or make entries in a trace table. Two types of inter-CPU interference are avoided by this invention compared to the prior S/370 tracing, which are:
Claim 16
Dependent Claim
14 words
No serializing interference occurs among the CPUs by not having any common trace-table header.
Claim 17
Dependent Claim
14 words
No serializing interference occurs among the CPUs by not having any common trace-table header.
Claim 18
Dependent Claim
71 words
No cross-cache interference occurs, since each CPU accesses a different interface and a different trace table. For example in the prior S/370 system trace table, a header field or trace entry required by a CPU may be part of a cache line in another CPU's cache; whereby the line must first be castout to the requesting CPUfs cache before the next entry address or new trace table entry can be written.
Claim 19
Dependent Claim
71 words
No cross-cache interference occurs, since each CPU accesses a different interface and a different trace table. For example in the prior S/370 system trace table, a header field or trace entry required by a CPU may be part of a cache line in another CPU's cache; whereby the line must first be castout to the requesting CPUfs cache before the next entry address or new trace table entry can be written.
Claim 20
Dependent Claim
62 words
Two types of tracing may cause entries to be made in a CPU's trace table: (1) implicit tracing of (a) a set of branch instructions, and (b) a set of ASN (address space number) instructions, and (2) explicit tracing by a novel general trace instruction. These sets may be less than all available branch instructions or less than all available ASN instructions.
Claim 21
Dependent Claim
62 words
Two types of tracing may cause entries to be made in a CPU's trace table: (1) implicit tracing of (a) a set of branch instructions, and (b) a set of ASN (address space number) instructions, and (2) explicit tracing by a novel general trace instruction. These sets may be less than all available branch instructions or less than all available ASN instructions.
Claim 22
Dependent Claim
32 words
In order to identify the length and type of each trace entry when examining a trace table, an entry identifier (ID) code is put into the first field of each trace entry.
Claim 23
Dependent Claim
32 words
In order to identify the length and type of each trace entry when examining a trace table, an entry identifier (ID) code is put into the first field of each trace entry.
Claim 24
Dependent Claim
14 words
Branch tracing, ASN tracing, and explicit tracing may be separately enabled in each CPU.
Claim 25
Dependent Claim
14 words
Branch tracing, ASN tracing, and explicit tracing may be separately enabled in each CPU.
Claim 26
Dependent Claim
71 words
When branch tracing is enabled and a traceable branch instruction is executed, an entry is made in the CPU's trace table if the branch is taken by the instruction. The ID code put into the trace entry also indicates which addressing mode is in effect after the branch is taken. When ASN tracing is enabled and a traceable ASN instruction is executed, an entry is made in the CPU's trace table.
Claim 27
Dependent Claim
71 words
When branch tracing is enabled and a traceable branch instruction is executed, an entry is made in the CPU's trace table if the branch is taken by the instruction. The ID code put into the trace entry also indicates which addressing mode is in effect after the branch is taken. When ASN tracing is enabled and a traceable ASN instruction is executed, an entry is made in the CPU's trace table.
Claim 28
Dependent Claim
65 words
When explicit tracing is enabled and a trace instruction is executed, an entry is made in the CPU's trace table. A trace instruction entry includes a time stamp taken from a system time-of-day (TOD) clock, a storage operand fetched by the executing trace instruction, contents of specified general registers, and a number field (N) which is one less than the number of specified general registers.
Claim 29
Dependent Claim
65 words
When explicit tracing is enabled and a trace instruction is executed, an entry is made in the CPU's trace table. A trace instruction entry includes a time stamp taken from a system time-of-day (TOD) clock, a storage operand fetched by the executing trace instruction, contents of specified general registers, and a number field (N) which is one less than the number of specified general registers.
Claim 30
Dependent Claim
71 words
The time stamp is valuable in the trace instruction entries due to the way this instruction is used for tracing. A time stamp is less valuable in the trace entries for the traceable instructions; and it is preferable for them not to contain a time stamp in a tradeoff between containing the time stamp and saving the storage space in the trace table by not having them use the time stamp.
Claim 31
Dependent Claim
71 words
The time stamp is valuable in the trace instruction entries due to the way this instruction is used for tracing. A time stamp is less valuable in the trace entries for the traceable instructions; and it is preferable for them not to contain a time stamp in a tradeoff between containing the time stamp and saving the storage space in the trace table by not having them use the time stamp.
Claim 32
Dependent Claim
94 words
Control over both implicit and explicit tracing is done in this invention on a CPU basis in a MP system by using one of the control registers (CRs) in each CPU. This tracing control register contains flag fields for controlling the enablement of the different types of tracing in a trace table for that CPU. The CR also contains a trace entry address field which stores the address of the next entry to be made in the trace table by the next executed enabled traceable or tracing instruction. These CR control fields may comprise:
Claim 33
Dependent Claim
94 words
Control over both implicit and explicit tracing is done in this invention on a CPU basis in a MP system by using one of the control registers (CRs) in each CPU. This tracing control register contains flag fields for controlling the enablement of the different types of tracing in a trace table for that CPU. The CR also contains a trace entry address field which stores the address of the next entry to be made in the trace table by the next executed enabled traceable or tracing instruction. These CR control fields may comprise:
Claim 34
Dependent Claim
37 words
A branch-trace-control bit (B) which controls whether implicit tracing for a set of branch instructions is enabled or disabled. If the bit is zero, branch tracing is disabled; if the bit is one, branch tracing is enabled.
Claim 35
Dependent Claim
37 words
A branch-trace-control bit (B) which controls whether implicit tracing for a set of branch instructions is enabled or disabled. If the bit is zero, branch tracing is disabled; if the bit is one, branch tracing is enabled.
Claim 36
Dependent Claim
38 words
ASN trace control bit (A) which controls whether implicit tracing for a set of ASN instructions is enabled or disabled. If the bit is zero, ASN tracing is disabled; if the bit is one, ASN tracing is enabled.
Claim 37
Dependent Claim
38 words
ASN trace control bit (A) which controls whether implicit tracing for a set of ASN instructions is enabled or disabled. If the bit is zero, ASN tracing is disabled; if the bit is one, ASN tracing is enabled.
Claim 38
Dependent Claim
81 words
An explicit trace control bit (E) controls whether tracing by the trace instruction is enabled or disabled. If the bit is zero, explicit tracing is disabled which causes the trace instruction to be executed as a no-operation (NOP); if the bit is one, the execution of the trace instruction creates an entry in the trace table, except that no entry is made when a disablement flag bit (T) in a storage operand of the particular trace instruction indicates it is disabled.
Claim 39
Dependent Claim
81 words
An explicit trace control bit (E) controls whether tracing by the trace instruction is enabled or disabled. If the bit is zero, explicit tracing is disabled which causes the trace instruction to be executed as a no-operation (NOP); if the bit is one, the execution of the trace instruction creates an entry in the trace table, except that no entry is made when a disablement flag bit (T) in a storage operand of the particular trace instruction indicates it is disabled.
Claim 40
Dependent Claim
57 words
The flag fields within any control register can be enabled in any combination or all be enabled or disabled. Also the tracing control registers for the different CPUs in a MP can have their flag fields set independently of each other, whereby tracing can be disabled in some CPUs and enabled in other CPUs in any combination.
Claim 41
Dependent Claim
57 words
The flag fields within any control register can be enabled in any combination or all be enabled or disabled. Also the tracing control registers for the different CPUs in a MP can have their flag fields set independently of each other, whereby tracing can be disabled in some CPUs and enabled in other CPUs in any combination.
Claim 42
Dependent Claim
86 words
When a traceable instruction is decoded for execution by a CPU and the corresponding implicit tracing function is enabled, a trace entry with an appropriate format is made in that CPU's trace table. The real address of each next trace entry is directly obtained from the CPU's tracing CR address field. After it is fetched, the address in the control register is increased by the size of the variable entry being created, in order to provide the address to the next entry in that trace table.
Claim 43
Dependent Claim
86 words
When a traceable instruction is decoded for execution by a CPU and the corresponding implicit tracing function is enabled, a trace entry with an appropriate format is made in that CPU's trace table. The real address of each next trace entry is directly obtained from the CPU's tracing CR address field. After it is fetched, the address in the control register is increased by the size of the variable entry being created, in order to provide the address to the next entry in that trace table.
Claim 44
Dependent Claim
91 words
Whenever a trace entry would cross a page boundary in main storage (e.g. the next address in the CR would be outside the current page frame), it is detected by a carry propagated into the page boundary bit position (e.g. bit 19 for a 4KB page), a trace-table exception signal is generated, and the instruction execution is nullified. After the next page frame is obtained, its address is put into the trace-controlling CR, and the instruction is re-executed to generate the trace entry at the beginning of the new page frame.
Claim 45
Dependent Claim
91 words
Whenever a trace entry would cross a page boundary in main storage (e.g. the next address in the CR would be outside the current page frame), it is detected by a carry propagated into the page boundary bit position (e.g. bit 19 for a 4KB page), a trace-table exception signal is generated, and the instruction execution is nullified. After the next page frame is obtained, its address is put into the trace-controlling CR, and the instruction is re-executed to generate the trace entry at the beginning of the new page frame.
Claim 46
Dependent Claim
65 words
The use of variable length entries: (1) allows all entries to contain all of the trace information required, and (2) avoids wasted space. The length of an entry is signalled by an identifier code field at the beginning of each trace table entry, which in some cases is followed by a byte count of the length of a variable field in that type of entry.
Claim 47
Dependent Claim
65 words
The use of variable length entries: (1) allows all entries to contain all of the trace information required, and (2) avoids wasted space. The length of an entry is signalled by an identifier code field at the beginning of each trace table entry, which in some cases is followed by a byte count of the length of a variable field in that type of entry.
Claim 48
Dependent Claim
125 words
Each decoded trace instruction fetches an operand from storage. A disablement bit position (T) in the storage operand is provided to allow any user to selectively disable any trace instruction after the instructions have been assembled into a program without having the user access the assembled program, which would be dangerous to its integrity. That is, the user only needs to access and change its operand data in main storage to selectively set on or off the disablement bits (T) in the operands of those trace instructions in the related program. When the disablement bit position in an operand is disabled, there is no trace entry to be made by the corresponding instruction, even though explicit tracing is enabled in the CPU's tracing control register.
Claim 49
Dependent Claim
125 words
Each decoded trace instruction fetches an operand from storage. A disablement bit position (T) in the storage operand is provided to allow any user to selectively disable any trace instruction after the instructions have been assembled into a program without having the user access the assembled program, which would be dangerous to its integrity. That is, the user only needs to access and change its operand data in main storage to selectively set on or off the disablement bits (T) in the operands of those trace instructions in the related program. When the disablement bit position in an operand is disabled, there is no trace entry to be made by the corresponding instruction, even though explicit tracing is enabled in the CPU's tracing control register.
Claim 50
Dependent Claim
57 words
It is possible for a plurality of trace instructions to address the same storage operand, in which case this plurality of trace instructions is controlled as a subset by one operand disablement flag T. But by having a unique operand location for each tracing instruction, each trace instruction can be individually controlled by a flag bit T.
Claim 51
Dependent Claim
57 words
It is possible for a plurality of trace instructions to address the same storage operand, in which case this plurality of trace instructions is controlled as a subset by one operand disablement flag T. But by having a unique operand location for each tracing instruction, each trace instruction can be individually controlled by a flag bit T.
Claim 52
Dependent Claim
48 words
Normally, the trace instructions may be "seeded" throughout a programming module during its compilation or assembly, and thereafter they are not easily located or changed. Their operands, on the other hand, can be assembled into tables in a data module that can be easily located and dynamically modified.
Claim 53
Dependent Claim
48 words
Normally, the trace instructions may be "seeded" throughout a programming module during its compilation or assembly, and thereafter they are not easily located or changed. Their operands, on the other hand, can be assembled into tables in a data module that can be easily located and dynamically modified.
Claim 54
Dependent Claim
77 words
With individual explicit instruction disabling, a user can dynamically control the tracing activities by changing the T bits to meet changing criteria, without impact to existing program modules. This provision for simple adjustment to accommodate unforeseen or changing needs: (1) contributes to the utility of a tracing facility, and (2) provides flexibility in: (a) dynamically establishing just how much tracing is to be done, and (b) in apportioning the tracing among the components of a programming system.
Claim 55
Dependent Claim
77 words
With individual explicit instruction disabling, a user can dynamically control the tracing activities by changing the T bits to meet changing criteria, without impact to existing program modules. This provision for simple adjustment to accommodate unforeseen or changing needs: (1) contributes to the utility of a tracing facility, and (2) provides flexibility in: (a) dynamically establishing just how much tracing is to be done, and (b) in apportioning the tracing among the components of a programming system.
Claim 56
Dependent Claim
102 words
This invention also allows a console operator to control the selection of which of plural classes of trace instructions will generate trace entries. This can be done after a class field is set in each storage operand of those trace instructions to be console controlled. By setting a different class (e.g. 0 to 15) in the storage operands (e.g. in bits 4 to 7 thereof) in different programs, or in different parts of a program, console control can be exercised by the console controlling the form of a TR mask set into the CPU to enable selected classes of the trace instructions.
Claim 57
Dependent Claim
102 words
This invention also allows a console operator to control the selection of which of plural classes of trace instructions will generate trace entries. This can be done after a class field is set in each storage operand of those trace instructions to be console controlled. By setting a different class (e.g. 0 to 15) in the storage operands (e.g. in bits 4 to 7 thereof) in different programs, or in different parts of a program, console control can be exercised by the console controlling the form of a TR mask set into the CPU to enable selected classes of the trace instructions.
Claim 58
Dependent Claim
33 words
Prior tracing mechanisms, by comparison, often have provided relatively too few or too many trace table entries for particular circumstances, and are less amenable to adjustment to bring them into balance with needs.
Claim 59
Dependent Claim
33 words
Prior tracing mechanisms, by comparison, often have provided relatively too few or too many trace table entries for particular circumstances, and are less amenable to adjustment to bring them into balance with needs.
Claim 60
Dependent Claim
127 words
Operating system performance often can be improved by changing the interface operation between modules by changing Supervisor Call (SVC) instructions to Branch and Link instructions to eliminate the hardware interrupt that the SVC causes. When such a change is made, the conventional branch trace information (generated by the SVC interruption handler program) is no longer obtained. Thus, as more and more Branch and Link interfaces are coded in the system, less and less trace information is gathered. The branch trace function of this invention provides the ability to regain the trace information without program interruption, except at occasional page boundary crossings. Since branch tracing is separately enabled in the tracing control register, the tracing information is gathered only when problems occur in this part of the system.
Claim 61
Dependent Claim
127 words
Operating system performance often can be improved by changing the interface operation between modules by changing Supervisor Call (SVC) instructions to Branch and Link instructions to eliminate the hardware interrupt that the SVC causes. When such a change is made, the conventional branch trace information (generated by the SVC interruption handler program) is no longer obtained. Thus, as more and more Branch and Link interfaces are coded in the system, less and less trace information is gathered. The branch trace function of this invention provides the ability to regain the trace information without program interruption, except at occasional page boundary crossings. Since branch tracing is separately enabled in the tracing control register, the tracing information is gathered only when problems occur in this part of the system.
Claim 62
Dependent Claim
32 words
The foregoing and other objects, features, and advantages of the invention will be apparent from the following detailed description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.
Claim 63
Dependent Claim
32 words
The foregoing and other objects, features, and advantages of the invention will be apparent from the following detailed description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.
Claim 64
Dependent Claim
5 words
BRIEF DESCRIPTION OF THE DRAWINGS
Claim 65
Dependent Claim
5 words
BRIEF DESCRIPTION OF THE DRAWINGS
Claim 66
Dependent Claim
133 words
FIGURE 1 illustrates the architecture for a trace instruction which is a subject of the present invention. FIGURE 2 illustrates different types of variable length entries which may be made in any CPU trace table for implicit tracing by certain branch and ASN instructions and explicit tracing by the trace instruction shown in FIGURE 1. FIGURE 3 is a logic diagram of hardware which may be found in a CPU to support the tracing operation by traceable and trace instructions. FIGURE 4 represents an instruction stream assembled to contain trace instructions. FIGURE 5 is a flow diagram of a method which may be used by the subject invention. FIGURE 6 illustrates substeps within step 103 in FIGURE 5. FIGURE 7 represents the prior art System/370 tracing architecture useable by a plurality of CPU's.
Claim 67
Dependent Claim
133 words
FIGURE 1 illustrates the architecture for a trace instruction which is a subject of the present invention. FIGURE 2 illustrates different types of variable length entries which may be made in any CPU trace table for implicit tracing by certain branch and ASN instructions and explicit tracing by the trace instruction shown in FIGURE 1. FIGURE 3 is a logic diagram of hardware which may be found in a CPU to support the tracing operation by traceable and trace instructions. FIGURE 4 represents an instruction stream assembled to contain trace instructions. FIGURE 5 is a flow diagram of a method which may be used by the subject invention. FIGURE 6 illustrates substeps within step 103 in FIGURE 5. FIGURE 7 represents the prior art System/370 tracing architecture useable by a plurality of CPU's.
Claim 68
Dependent Claim
6 words
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Claim 69
Dependent Claim
6 words
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Claim 70
Dependent Claim
84 words
FIGURE 1 illustrates the architecture for a trace instruction 11 comprising a special operation code (TR OP CODE) and three operand addresses, of which Rl and R3 define the bounds of a range of general purpose registers (GRs) in a System/370 CPU from Rl through R3 with wraparound. The second operand address comprises B2 and D2, which are combined to provide a logical address (which may be a virtual address) of the second operand (OPD2) which is a 32 bit word in main storage.
Claim 71
Dependent Claim
84 words
FIGURE 1 illustrates the architecture for a trace instruction 11 comprising a special operation code (TR OP CODE) and three operand addresses, of which Rl and R3 define the bounds of a range of general purpose registers (GRs) in a System/370 CPU from Rl through R3 with wraparound. The second operand address comprises B2 and D2, which are combined to provide a logical address (which may be a virtual address) of the second operand (OPD2) which is a 32 bit word in main storage.
Claim 72
Dependent Claim
64 words
Any number of trace (TR) instructions of the type shown as 11 in FIGURE 1 may be inserted at selected tracing locations in an instruction stream of any program written in compliance with the IBM System/370 Extended Architecture (XA), see the IBM System/370 Extended Architecture Principles of Operation, Form No. SA22-7085. FIGURE 4 illustrates an example of a program having TR instructions sprinkled throughout.
Claim 73
Dependent Claim
64 words
Any number of trace (TR) instructions of the type shown as 11 in FIGURE 1 may be inserted at selected tracing locations in an instruction stream of any program written in compliance with the IBM System/370 Extended Architecture (XA), see the IBM System/370 Extended Architecture Principles of Operation, Form No. SA22-7085. FIGURE 4 illustrates an example of a program having TR instructions sprinkled throughout.
Claim 74
Dependent Claim
118 words
One of the control registers (CRs) of the 16 in each CPU (designated as CR12) is used to control the tracing operation. In CR12, there are three flag fields designated as B, A, and E, which are each a single bit in length. Also, CR12 contains an address field designated as the next TT (trace table) entry address. Flag bit B (when set to a one state) enables the implicit tracing of the following set of S/370XA instructions: BRANCH AND LINK (BALR format only) when the R2 field is not zero, i.e. when the BALR instruction specifies a GR wherein the branch address is stored. BRANCH AND SAVE (BASR format only) when the R2 field is not zero.
Claim 75
Dependent Claim
118 words
One of the control registers (CRs) of the 16 in each CPU (designated as CR12) is used to control the tracing operation. In CR12, there are three flag fields designated as B, A, and E, which are each a single bit in length. Also, CR12 contains an address field designated as the next TT (trace table) entry address. Flag bit B (when set to a one state) enables the implicit tracing of the following set of S/370XA instructions: BRANCH AND LINK (BALR format only) when the R2 field is not zero, i.e. when the BALR instruction specifies a GR wherein the branch address is stored. BRANCH AND SAVE (BASR format only) when the R2 field is not zero.
Claim 76
Dependent Claim
13 words
BRANCH AND SAVE AND SET MODE when the R2 field is not zero.
Claim 77
Dependent Claim
13 words
BRANCH AND SAVE AND SET MODE when the R2 field is not zero.
Claim 78
Dependent Claim
68 words
When their tracing is enabled by B being one, each time one of these branch instructions is executed, a trace entry is generated and inserted into a trace table for the respective CPU in main storage as a 31 bit branch entry or a 24 bit branch entry of the type shown in FIGURE 2 in accordance with the S/370XA address mode existing after a branch is taken.
Claim 79
Dependent Claim
68 words
When their tracing is enabled by B being one, each time one of these branch instructions is executed, a trace entry is generated and inserted into a trace table for the respective CPU in main storage as a 31 bit branch entry or a 24 bit branch entry of the type shown in FIGURE 2 in accordance with the S/370XA address mode existing after a branch is taken.
Claim 80
Dependent Claim
34 words
In a similar manner, when flag bit A is set to one, it enables the implicit tracing of the following set of S/370XA address space ASN instructions: PROGRAM CALL PROGRAM TRANSFER SET SECONDARY ASN
Claim 81
Dependent Claim
34 words
In a similar manner, when flag bit A is set to one, it enables the implicit tracing of the following set of S/370XA address space ASN instructions: PROGRAM CALL PROGRAM TRANSFER SET SECONDARY ASN
Claim 82
Dependent Claim
52 words
When bit A is set to 1, an entry is made in the trace table upon execution of any of these ASN instructions. The format of the trace entries respectively generated in the trace table for these ASN instructions also is illustrated in FIGURE 2 with the name of the respective instruction.
Claim 83
Dependent Claim
52 words
When bit A is set to 1, an entry is made in the trace table upon execution of any of these ASN instructions. The format of the trace entries respectively generated in the trace table for these ASN instructions also is illustrated in FIGURE 2 with the name of the respective instruction.
Claim 84
Dependent Claim
65 words
The setting to a one state of either flag bit B or A or both enables implicit tracing, because a trace table entry is then generated implicitly as part of the execution process whenever any instruction in these two sets is executed. It is implicit, because the programmer who put these instructions into a program need not have been aware of their later tracing use.
Claim 85
Dependent Claim
65 words
The setting to a one state of either flag bit B or A or both enables implicit tracing, because a trace table entry is then generated implicitly as part of the execution process whenever any instruction in these two sets is executed. It is implicit, because the programmer who put these instructions into a program need not have been aware of their later tracing use.
Claim 86
Dependent Claim
150 words
On the other hand, flag bit E in CR12 controls explicit tracing by each trace instruction of the type represented as 11 in FIGURE 1, which will generate entries in the trace table having the format labeled TRACE in FIGURE 2. The use of the TR instruction by a programmer is explicit because the programmer will knowingly put it in a program for tracing purposes. While explicit tracing is enabled (i.e. flag bit E is set to 1) and a trace instruction 11 is encountered in an executing program, any particular trace instruction may still be disabled and not generate any trace entry if its flag bit T is set to zero state in the second operand 12 of the trace instruction. However, if flag bit T is set to a one state, then the instruction is enabled and a trace entry is generated and put into the trace tabel.
Claim 87
Dependent Claim
150 words
On the other hand, flag bit E in CR12 controls explicit tracing by each trace instruction of the type represented as 11 in FIGURE 1, which will generate entries in the trace table having the format labeled TRACE in FIGURE 2. The use of the TR instruction by a programmer is explicit because the programmer will knowingly put it in a program for tracing purposes. While explicit tracing is enabled (i.e. flag bit E is set to 1) and a trace instruction 11 is encountered in an executing program, any particular trace instruction may still be disabled and not generate any trace entry if its flag bit T is set to zero state in the second operand 12 of the trace instruction. However, if flag bit T is set to a one state, then the instruction is enabled and a trace entry is generated and put into the trace tabel.
Claim 88
Dependent Claim
125 words
An optional class control facility may also be provided in the CPU to control class enablement and disablement of trace instructions. For example, all of the trace instructions in one routine may be designated as class 1 while all trace instructions in another routine may be designated as class 2. Then if the class facility is available in the CPU, the console operator can set a trace mask into a trace mask register in the CPU (shown as item 22 in FIGURE 3) to, for example, enable class 1 and disable class 2. This will cause only class 1 trace instructions to put entries in the trace table, and class 2 trace instructions will then execute as no-operations (NOPs) and not provide any trace entries.
Claim 89
Dependent Claim
125 words
An optional class control facility may also be provided in the CPU to control class enablement and disablement of trace instructions. For example, all of the trace instructions in one routine may be designated as class 1 while all trace instructions in another routine may be designated as class 2. Then if the class facility is available in the CPU, the console operator can set a trace mask into a trace mask register in the CPU (shown as item 22 in FIGURE 3) to, for example, enable class 1 and disable class 2. This will cause only class 1 trace instructions to put entries in the trace table, and class 2 trace instructions will then execute as no-operations (NOPs) and not provide any trace entries.
Claim 90
Dependent Claim
110 words
The integrity of a program capable of being traced is enhanced by putting special tracing enablement/disablement control into the storage operand of each trace instruction. This is done by having the second operand data located in a different program control section than the program module containing the trace instructions 11. Then the user can later control the disablement of any trace instruction setting either or both of its flag bit T, and/or its class field (if any) without disturbing the program module. By avoiding having the user access the program, its integrity is maintained, since it could be destroyed if users were allowed to reassemble the module for controlling tracing.
Claim 91
Dependent Claim
110 words
The integrity of a program capable of being traced is enhanced by putting special tracing enablement/disablement control into the storage operand of each trace instruction. This is done by having the second operand data located in a different program control section than the program module containing the trace instructions 11. Then the user can later control the disablement of any trace instruction setting either or both of its flag bit T, and/or its class field (if any) without disturbing the program module. By avoiding having the user access the program, its integrity is maintained, since it could be destroyed if users were allowed to reassemble the module for controlling tracing.
Claim 92
Dependent Claim
34 words
Also, a comment field is provided in the storage operand shown as 12 in Fig. 1 which a user may also set, in contemplation of doing a particular trace without accessing the program itself.
Claim 93
Dependent Claim
34 words
Also, a comment field is provided in the storage operand shown as 12 in Fig. 1 which a user may also set, in contemplation of doing a particular trace without accessing the program itself.
Claim 94
Dependent Claim
129 words
FIGURE 3 illustrates those circuits 20 within each CPU which are important to the subject invention. It is obvious that any CPU contains a tremendous amount of circuitry of a conventional nature to perform normal functions of the CPU not important in describing an embodiment of the subject invention, and they are not shown or discussed herein because they would clutter the communication of the inventive concepts. Thus, in FIGURE 3 each CPU has a time-of-day (TOD) clock 21, instruction execution (IE) means 23, TR mask register 22, control registers (CRs) 0 through 15 (of which the CR12 output is shown), GRs (general purpose registers) 0 through 15, TR data register 26, storage data bus (SDB) register 31, storage address bus (SAB) register 32, etc., and interconnecting circuitry representations.
Claim 95
Dependent Claim
129 words
FIGURE 3 illustrates those circuits 20 within each CPU which are important to the subject invention. It is obvious that any CPU contains a tremendous amount of circuitry of a conventional nature to perform normal functions of the CPU not important in describing an embodiment of the subject invention, and they are not shown or discussed herein because they would clutter the communication of the inventive concepts. Thus, in FIGURE 3 each CPU has a time-of-day (TOD) clock 21, instruction execution (IE) means 23, TR mask register 22, control registers (CRs) 0 through 15 (of which the CR12 output is shown), GRs (general purpose registers) 0 through 15, TR data register 26, storage data bus (SDB) register 31, storage address bus (SAB) register 32, etc., and interconnecting circuitry representations.
Claim 96
Dependent Claim
121 words
The TR mask register 22 is an optional feature of a CPU which is only needed to support the class tracing control previously described, which may not exist on other CPU's. If it does not exist, the class field (bits 4-7) in OPD2 shown in FIGURE 1 cannot be used, and is ignored by the CPU. If the TR mask register 22 does exist in the CPU, it is set by a set trace mask command from the system console (not shown), which is called a processor controller (PC) in some systems. See European application No. for a description of a PC connected to a plurality of CPU's in an MP having TR mask registers set by set trace mask commands.
Claim 97
Dependent Claim
121 words
The TR mask register 22 is an optional feature of a CPU which is only needed to support the class tracing control previously described, which may not exist on other CPU's. If it does not exist, the class field (bits 4-7) in OPD2 shown in FIGURE 1 cannot be used, and is ignored by the CPU. If the TR mask register 22 does exist in the CPU, it is set by a set trace mask command from the system console (not shown), which is called a processor controller (PC) in some systems. See European application No. for a description of a PC connected to a plurality of CPU's in an MP having TR mask registers set by set trace mask commands.
Claim 98
Dependent Claim
68 words
The CPU receives commands from the PC on a bidirectional bus 36, which is connected to a PC command decoder 37 and an AND gate 38. When decoder 37 receives and decodes a set trace mask command, it enables gate 38 to pass a trace mask (then being sent on PC bus 36) of 16 bits which are loaded into the trace mask register 22 of the CPU.
Claim 99
Dependent Claim
68 words
The CPU receives commands from the PC on a bidirectional bus 36, which is connected to a PC command decoder 37 and an AND gate 38. When decoder 37 receives and decodes a set trace mask command, it enables gate 38 to pass a trace mask (then being sent on PC bus 36) of 16 bits which are loaded into the trace mask register 22 of the CPU.
Claim 100
Dependent Claim
30 words
A different TR mask command is recognized by each CPU in the system, so that the PC can differently set the TR masks in the different CPUs of a MP.
Claim 101
Dependent Claim
30 words
A different TR mask command is recognized by each CPU in the system, so that the PC can differently set the TR masks in the different CPUs of a MP.
Claim 102
Dependent Claim
21 words
Thus, a set TR mask command to any CPU loads its TR mask register 22 via bus 36 from the PC.
Claim 103
Dependent Claim
21 words
Thus, a set TR mask command to any CPU loads its TR mask register 22 via bus 36 from the PC.
Claim 104
Dependent Claim
38 words
The instruction execution (IE) means 23 of each CPU interprets and executes the instruction stream of the CPU in a conventional manner. Additionally, the IE executes the novel implicit tracing and explicit tracing (TR) instruction as described herein.
Claim 105
Dependent Claim
38 words
The instruction execution (IE) means 23 of each CPU interprets and executes the instruction stream of the CPU in a conventional manner. Additionally, the IE executes the novel implicit tracing and explicit tracing (TR) instruction as described herein.
Claim 106
Independent Claim
84 words
A system performance advantage of this invention is that a CPU does not interrupt the instruction stream when using the implicit and explicit tracing taught by this invention. (Occasionally an interrupt is required to allocate a new page to continue the trace table when the current page becomes filled with trace entries. Page allocation type interrupts are well known in virtual address systems, such as in the IBM Multiple Virtual Storage (MVS) control programming. Note that a paging interrupt is not a tracing interrupt.)
Claim 107
Independent Claim
84 words
A system performance advantage of this invention is that a CPU does not interrupt the instruction stream when using the implicit and explicit tracing taught by this invention. (Occasionally an interrupt is required to allocate a new page to continue the trace table when the current page becomes filled with trace entries. Page allocation type interrupts are well known in virtual address systems, such as in the IBM Multiple Virtual Storage (MVS) control programming. Note that a paging interrupt is not a tracing interrupt.)
Claim 108
Dependent Claim
116 words
The CPU execution of a TR instruction in the IE in FIGURE 3 involves the IE providing the TR second operand absolute address (after any translation and prefixing) on bus 41 via an OR circuit 42 to SAB (storage address bus) register 32 in order to access the second operand in a CPU cache (not shown), or if not in the cache, from main storage. (Cache and storage access controls may be conventional, which are well known in the art.) A storage data bus out (SDBO) 43 receives the operand data from the cache (or from main storage) and transfers it to IE 23. The IE temporarily stores the second operand in its local store 44.
Claim 109
Dependent Claim
116 words
The CPU execution of a TR instruction in the IE in FIGURE 3 involves the IE providing the TR second operand absolute address (after any translation and prefixing) on bus 41 via an OR circuit 42 to SAB (storage address bus) register 32 in order to access the second operand in a CPU cache (not shown), or if not in the cache, from main storage. (Cache and storage access controls may be conventional, which are well known in the art.) A storage data bus out (SDBO) 43 receives the operand data from the cache (or from main storage) and transfers it to IE 23. The IE temporarily stores the second operand in its local store 44.
Claim 110
Dependent Claim
87 words
FIGURES 5 and 6 represent a microcode method used in the CPU shown in FIGURE 3 for controlling the execution of implicit and explicit tracing. This execution process uses local store 44 to contain temporary results of IE operations. The microcode causes the transmission of selected contents of local store 44 to TR data register 26 for transmission to main storage for writing a trace table entry. FIGURES 5 and 6 apply to each CPU in a MP system and operate independently in each of the CPUs.
Claim 111
Dependent Claim
87 words
FIGURES 5 and 6 represent a microcode method used in the CPU shown in FIGURE 3 for controlling the execution of implicit and explicit tracing. This execution process uses local store 44 to contain temporary results of IE operations. The microcode causes the transmission of selected contents of local store 44 to TR data register 26 for transmission to main storage for writing a trace table entry. FIGURES 5 and 6 apply to each CPU in a MP system and operate independently in each of the CPUs.
Claim 112
Dependent Claim
134 words
In FIGURE 5, after the CPU is started, step 111 is entered to execute the next instruction, after which steps 112, 113 and 114 are entered to test whether the instruction is one of the types which can generate an implicit or explicit trace table entry. Step 112 tests to determine if it is any traceable instruction in the branch instruction set. Step 113 tests if it is a traceable instruction in the address space instruction set, and step 114 tests if it is a trace instruction. If all tests 112, 113, and 114 take their NO exits, step 111 is re-entered to execute the next instruction for the trace enablement condition. (All conventional instruction execution is also being done, but it is not pertinent to this invention and therefore is not described herein.)
Claim 113
Dependent Claim
134 words
In FIGURE 5, after the CPU is started, step 111 is entered to execute the next instruction, after which steps 112, 113 and 114 are entered to test whether the instruction is one of the types which can generate an implicit or explicit trace table entry. Step 112 tests to determine if it is any traceable instruction in the branch instruction set. Step 113 tests if it is a traceable instruction in the address space instruction set, and step 114 tests if it is a trace instruction. If all tests 112, 113, and 114 take their NO exits, step 111 is re-entered to execute the next instruction for the trace enablement condition. (All conventional instruction execution is also being done, but it is not pertinent to this invention and therefore is not described herein.)
Claim 114
Dependent Claim
165 words
However, if any of steps 112, l13 or 114 finds that the instruction is a traceable or trace instruction, then the YES exit is taken from the respective step, and the respective flag bit B, A, or E is tested to determine if it is set to a 1 state or 0 state. If the flag bit is set to a 0 state, then the NO exit is taken from the test step back to step 111 to execute the next instruction for its trace enablement condition. However, if the tested flag bit B, A, or E is found to be in a 1 state, then the test step's YES exit is taken. If the YES exit is taken from the test step l16 or 117 for flag bit B or A, then step 104 or 105 is entered, respectively, for controlling the writing of a trace table entry in accordance with the corresponding format shown in FIGURE 2 for the respective instruction being executed.
Claim 115
Dependent Claim
165 words
However, if any of steps 112, l13 or 114 finds that the instruction is a traceable or trace instruction, then the YES exit is taken from the respective step, and the respective flag bit B, A, or E is tested to determine if it is set to a 1 state or 0 state. If the flag bit is set to a 0 state, then the NO exit is taken from the test step back to step 111 to execute the next instruction for its trace enablement condition. However, if the tested flag bit B, A, or E is found to be in a 1 state, then the test step's YES exit is taken. If the YES exit is taken from the test step l16 or 117 for flag bit B or A, then step 104 or 105 is entered, respectively, for controlling the writing of a trace table entry in accordance with the corresponding format shown in FIGURE 2 for the respective instruction being executed.
Claim 116
Dependent Claim
50 words
Steps 104 and 105 determine if the new entry having the length shown in FIGURE 2 will exceed the end of the currently used page frame, and if so, step 104 or 105 will allocate a new page frame, which then becomes the address of the next entry in CR12.
Claim 117
Dependent Claim
50 words
Steps 104 and 105 determine if the new entry having the length shown in FIGURE 2 will exceed the end of the currently used page frame, and if so, step 104 or 105 will allocate a new page frame, which then becomes the address of the next entry in CR12.
Claim 118
Dependent Claim
76 words
Then step 106 or 107 each generate a respective entry ID code for the leftmost field of the entry to be written (as shown in FIGURE 2). This entry ID code enables the length and type of each written trace table entry to be determined during later analysis of the table, since the written entries may have different lengths. Then step 108 or 109 writes the entry at the next entry location in the trace table.
Claim 119
Dependent Claim
76 words
Then step 106 or 107 each generate a respective entry ID code for the leftmost field of the entry to be written (as shown in FIGURE 2). This entry ID code enables the length and type of each written trace table entry to be determined during later analysis of the table, since the written entries may have different lengths. Then step 108 or 109 writes the entry at the next entry location in the trace table.
Claim 120
Dependent Claim
147 words
However, if the YES exit is taken from test step 118 for flag bit E, then the second operand (OPD2) is addressed and fetched by step 119. When received on storage data bus out (SDBO) 43 in FIGURE 3 into IE 23, it is put temporarily into local store 44 where the IE then executes step 121 to test the state of flag bit T to determine if it is in a 1 or 0 state. If in a 0 state, the trace instruction is disabled, and the NO exit is taken to step 111 to execute the next instruction for trace conditions. However, if flag bit T is in a 1 state, the YES exit is taken on path 101 to step 103 which writes the trace table (TT) entry. Then path 102 is taken to step 111 to execute the next instruction for trace conditions.
Claim 121
Dependent Claim
147 words
However, if the YES exit is taken from test step 118 for flag bit E, then the second operand (OPD2) is addressed and fetched by step 119. When received on storage data bus out (SDBO) 43 in FIGURE 3 into IE 23, it is put temporarily into local store 44 where the IE then executes step 121 to test the state of flag bit T to determine if it is in a 1 or 0 state. If in a 0 state, the trace instruction is disabled, and the NO exit is taken to step 111 to execute the next instruction for trace conditions. However, if flag bit T is in a 1 state, the YES exit is taken on path 101 to step 103 which writes the trace table (TT) entry. Then path 102 is taken to step 111 to execute the next instruction for trace conditions.
Claim 122
Dependent Claim
88 words
FIGURE 6 illustrates in more detail the substeps which comprise step 103 in FIGURE 5. In FIGURE 6, step 131 accesses a bit position in the address field in CR12 which corresponds to bit position 19 in the main storage absolute address designating the location for the trace entry intended to be made by the current trace instruction being executed on this CPU. This bit position 19 in CR12 is designated as current bit 19 in step 131, and it may be temporarily copied into local store 44.
Claim 123
Dependent Claim
88 words
FIGURE 6 illustrates in more detail the substeps which comprise step 103 in FIGURE 5. In FIGURE 6, step 131 accesses a bit position in the address field in CR12 which corresponds to bit position 19 in the main storage absolute address designating the location for the trace entry intended to be made by the current trace instruction being executed on this CPU. This bit position 19 in CR12 is designated as current bit 19 in step 131, and it may be temporarily copied into local store 44.
Claim 124
Dependent Claim
157 words
Then step 132 generates a value N which is one less than the number of registers in the sequence defined by the Rl and R3 fields in the executing trace instruction. The sequence begins with Rl and ends with R3. Rl and R3 can each have any value from 0 through 15. The sequence will wraparound back to GRO if R3 is less than Rl. If Rl and R3 are equal, one general register is designated and N is zero. If R3 is equal to or greater than Rl, then N equals R3 minus Rl. But if R3 is less than Rl, wraparound occurs and then N equals 16 minus Rl plus R3. Since N is one less than the number of registers specified by the R1 to R3 range in the instruction, it is necessary to add 1 to N in order to determine the number of registers in the range specified by the trace instruction.
Claim 125
Dependent Claim
157 words
Then step 132 generates a value N which is one less than the number of registers in the sequence defined by the Rl and R3 fields in the executing trace instruction. The sequence begins with Rl and ends with R3. Rl and R3 can each have any value from 0 through 15. The sequence will wraparound back to GRO if R3 is less than Rl. If Rl and R3 are equal, one general register is designated and N is zero. If R3 is equal to or greater than Rl, then N equals R3 minus Rl. But if R3 is less than Rl, wraparound occurs and then N equals 16 minus Rl plus R3. Since N is one less than the number of registers specified by the R1 to R3 range in the instruction, it is necessary to add 1 to N in order to determine the number of registers in the range specified by the trace instruction.
Claim 126
Dependent Claim
110 words
The next step 133 generates the address of the next trace entry, which will logically follow the entry currently being made in the trace table. This next address is generated as the current TT address (obtained from CR12) plus 12 plus the product of 4 multiplied by (N plus 1). That is, the length of a trace table entry for an explicit trace instruction is always 12 bytes plus the variable GR content field. This is seen in the trace entry shown in FIGURE 2, which illustrates bit positions, which must be converted to eight-bit bytes (ignoring parity) for the computation in step 133 (since addresses are in byte units).
Claim 127
Dependent Claim
110 words
The next step 133 generates the address of the next trace entry, which will logically follow the entry currently being made in the trace table. This next address is generated as the current TT address (obtained from CR12) plus 12 plus the product of 4 multiplied by (N plus 1). That is, the length of a trace table entry for an explicit trace instruction is always 12 bytes plus the variable GR content field. This is seen in the trace entry shown in FIGURE 2, which illustrates bit positions, which must be converted to eight-bit bytes (ignoring parity) for the computation in step 133 (since addresses are in byte units).
Claim 128
Dependent Claim
29 words
Then step 134 stores the next bit 19 from this computed next entry address (generated by step 133) into local store 44 at a location called next bit 19.
Claim 129
Dependent Claim
29 words
Then step 134 stores the next bit 19 from this computed next entry address (generated by step 133) into local store 44 at a location called next bit 19.
Claim 130
Dependent Claim
193 words
Step 136 compares current bit 19 and next bit 19 in local store 44. This determines if the current trace entry to be written would exceed the end boundary of the current page frame being used in main storage. This is done in step 136 by the IE. If current bit 19 and next bit 19 are equal (which is the usual case), then there is space in the current page for the current entry to be written; and it will then be written therein by entering step 137. Step 137 generates the current entry. This includes generating the entry ID code, which is done by the IE using the operation code and addressing mode resulting from the instruction being currently executed as an argument into a table of entry ID codes in local store 44. That is, each of the traceable instructions has an ID code which corresponds to its operation code except the traceable branch instructions which also require the branch-taken addressing mode. The accessed entry ID code in the table is then put into the ID code field (leftmost field) in the TT entry being formed in local store 44.
Claim 131
Dependent Claim
193 words
Step 136 compares current bit 19 and next bit 19 in local store 44. This determines if the current trace entry to be written would exceed the end boundary of the current page frame being used in main storage. This is done in step 136 by the IE. If current bit 19 and next bit 19 are equal (which is the usual case), then there is space in the current page for the current entry to be written; and it will then be written therein by entering step 137. Step 137 generates the current entry. This includes generating the entry ID code, which is done by the IE using the operation code and addressing mode resulting from the instruction being currently executed as an argument into a table of entry ID codes in local store 44. That is, each of the traceable instructions has an ID code which corresponds to its operation code except the traceable branch instructions which also require the branch-taken addressing mode. The accessed entry ID code in the table is then put into the ID code field (leftmost field) in the TT entry being formed in local store 44.
Claim 132
Dependent Claim
28 words
This entry being formed in local store 44 by step 137 for a trace instruction also receives the TOD value from the TOD clock 21 in FIGURE 3.
Claim 133
Dependent Claim
28 words
This entry being formed in local store 44 by step 137 for a trace instruction also receives the TOD value from the TOD clock 21 in FIGURE 3.
Claim 134
Dependent Claim
79 words
Step 137 also inserts in the N field of the TT entry being formed in local store 44 the value of N as generated in step 132. Then step 138 accesses main storage. Then step 139 transfers the entry ID code, N field, TOD field, and second operand (fetched in step 119) from local store 44 via the TR data register 26 and SDB register 31 to the CPU cache and then to main storage into the trace table.
Claim 135
Dependent Claim
79 words
Step 137 also inserts in the N field of the TT entry being formed in local store 44 the value of N as generated in step 132. Then step 138 accesses main storage. Then step 139 transfers the entry ID code, N field, TOD field, and second operand (fetched in step 119) from local store 44 via the TR data register 26 and SDB register 31 to the CPU cache and then to main storage into the trace table.
Claim 136
Dependent Claim
39 words
Then step 139 transfers the contents of registers Rl through R3 as shown in the trace instruction format of FIGURE 2. In this manner, the TT entry may be written as the next trace entry in the trace table.
Claim 137
Dependent Claim
39 words
Then step 139 transfers the contents of registers Rl through R3 as shown in the trace instruction format of FIGURE 2. In this manner, the TT entry may be written as the next trace entry in the trace table.
Claim 138
Dependent Claim
37 words
Then step 140 takes the next entry address (which was generated and put into local store 44 by prior step 133) and transfers it from local store 44 into the next TT entry address field in CR12.
Claim 139
Dependent Claim
37 words
Then step 140 takes the next entry address (which was generated and put into local store 44 by prior step 133) and transfers it from local store 44 into the next TT entry address field in CR12.
Claim 140
Dependent Claim
81 words
However, if step 136 found an unequal comparison (i.e. current bit 19 and next bit 19 are different), then step 144 is entered because the trace entry being generated will exceed the end boundary of the current page frame being used. That is, the trace table has run out of allocated space in real storage and more space must be allocated before the trace table can be extended by another entry. To do this, step 144 generates a page exception signal.
Claim 141
Dependent Claim
81 words
However, if step 136 found an unequal comparison (i.e. current bit 19 and next bit 19 are different), then step 144 is entered because the trace entry being generated will exceed the end boundary of the current page frame being used. That is, the trace table has run out of allocated space in real storage and more space must be allocated before the trace table can be extended by another entry. To do this, step 144 generates a page exception signal.
Claim 142
Dependent Claim
28 words
Then step 145 nullifies the execution results for the executing TR instruction such as by nullifying those areas in the local store generated by the trace instruction execution.
Claim 143
Dependent Claim
28 words
Then step 145 nullifies the execution results for the executing TR instruction such as by nullifying those areas in the local store generated by the trace instruction execution.
Claim 144
Dependent Claim
154 words
Then a program interrupt is taken by step 146, and step 147 enters the storage allocation program which then allocates a new page frame for the trace table. Step 147 loads the new page address into the CR12 next TT entry address field. Finally exit A is taken to reenter FIGURE 5, wherein the microcode for the same TR instruction is restarted from its beginning after CPU control is transferred back to its program from the storage allocation program by the latter loading a PSW that causes the transfer back. The re-execution of the microcode in FIGURES 5 and 6 occurs in the same manner as previously described, except that when step 136 is entered it will find that the entry will fit into the allocated page frame, and step 137 will be entered to cause the writing of the trace entry into the trace table at the new page address now in CR12.
Claim 145
Dependent Claim
154 words
Then a program interrupt is taken by step 146, and step 147 enters the storage allocation program which then allocates a new page frame for the trace table. Step 147 loads the new page address into the CR12 next TT entry address field. Finally exit A is taken to reenter FIGURE 5, wherein the microcode for the same TR instruction is restarted from its beginning after CPU control is transferred back to its program from the storage allocation program by the latter loading a PSW that causes the transfer back. The re-execution of the microcode in FIGURES 5 and 6 occurs in the same manner as previously described, except that when step 136 is entered it will find that the entry will fit into the allocated page frame, and step 137 will be entered to cause the writing of the trace entry into the trace table at the new page address now in CR12.
Claim 146
Dependent Claim
51 words
It is understood that the microcode (i.e. firmware) process described herein could with relative ease by one skilled in the computer design arts be embodied solely in hardware or in any combination of microcode and hardware, and that the microcode form will vary in dependence on each particular support hardware design.
Claim 147
Dependent Claim
51 words
It is understood that the microcode (i.e. firmware) process described herein could with relative ease by one skilled in the computer design arts be embodied solely in hardware or in any combination of microcode and hardware, and that the microcode form will vary in dependence on each particular support hardware design.
Claim 148
Dependent Claim
47 words
While there has thus been described and illustrated a specific embodiment of the invention, it will be clear that variations in the details of the embodiment specifically illustrated and described may be made therein without departing from the scope of the invention as defined in the claims.
Claim 149
Dependent Claim
177 words
A program tracing method for each CPU in a data processing system having at least one CPU, a main storage accessed by each CPU, each CPU (20) having an instruction execution (IE) unit (23) for executing instructions in a program dispatched to the CPU, the IE having control registers (CRs) and general registers (GRs), the program tracing method characterized by: providing one (CR12) of the CRs in each CPU as a tracing control CR having a trace-entry-address field and at least a trace-instruction-control flag field (E), testing (112-114) each instruction being executed by the IE to indicate if it is a trace instruction, forming (106, 107, 137) fields for a trace entry (16) by the IE when the testing step indicates a trace instruction, inserting (108, 109, 103, 139) the trace entry obtained from the forming step into a trace table in main storage at an address provided by the trace-entry-address field of the tracing-control CR when the testing step indicates a trace instruction is being executed and the trace-instruction-control flag field is in an enabled state.
Claim 150
Dependent Claim
177 words
A program tracing method for each CPU in a data processing system having at least one CPU, a main storage accessed by each CPU, each CPU (20) having an instruction execution (IE) unit (23) for executing instructions in a program dispatched to the CPU, the IE having control registers (CRs) and general registers (GRs), the program tracing method characterized by: providing one (CR12) of the CRs in each CPU as a tracing control CR having a trace-entry-address field and at least a trace-instruction-control flag field (E), testing (112-114) each instruction being executed by the IE to indicate if it is a trace instruction, forming (106, 107, 137) fields for a trace entry (16) by the IE when the testing step indicates a trace instruction, inserting (108, 109, 103, 139) the trace entry obtained from the forming step into a trace table in main storage at an address provided by the trace-entry-address field of the tracing-control CR when the testing step indicates a trace instruction is being executed and the trace-instruction-control flag field is in an enabled state.
Claim 151
Dependent Claim
106 words
A program tracing method as defined in Claim 1, further comprising: accessing (119) a storage operand (12) by the IE executing an operand address field in a trace instruction (11) when the trace-instruction-control flag field (E) is enabled, a disablement flag field (T) being contained in the said storage operand (12), detecting (121) by the IE of the state of the disablement flag field in the storage operand to prevent the inserting step (103) from inserting the trace entry into the trace table when the disablement flag field indicates a disabled state, but allowing the inserting step when the disablement flag field indicates an enabled state.
Claim 152
Dependent Claim
39 words
A program tracing method as defined in Claim 2, further comprising: storing by the IE of at least part of the storage operand (12) into a trace entry (16) being formed by the IE for the trace instruction (11).
Claim 153
Dependent Claim
155 words
A program tracing method as defined in Claim 2 or 3, further comprising: determining by the IE (23) of a value in a class field in the storage operand (12), a trace mask register (22) in each or at least one CPU for being set with a class mask provided by a user of the data processing system, mask fields in the class mask in the trace mask register respectively controlling the enablement of respective tracing classes for the respective CPU, locating by the IE of a mask field in the trace mask register at a location dependent on the class field value provided by the determining step, and sensing the state of the mask field located by the locating step to find if the class field is enabling or disabling the executing trace instruction, whereby the trace entry is inserted into the trace table when all enablement conditions exist for the executing trace instruction.
Claim 154
Dependent Claim
48 words
A program tracing method as defined in Claims 2, 3 or 4, further comprising: recording a current time-of-day (TOD) value into a trace entry (16) being generated by the IE for the executing trace instruction, the TOD value being obtained from a TOD clock (21) in the system.
Claim 155
Dependent Claim
55 words
A program tracing method as defined in Claim 5, further comprising: also recording (139) the content of a general register (GR) or a range of GRs by the IE in the trace entry being formed, the GR or range of GRs being specified by bounding GR operand fields in the trace instruction (11) being executed.
Claim 156
Dependent Claim
56 words
A program tracing method as defined in Claim 6, further comprising: generating (132) by the IE a GR count of a number (N) dependent on the number of GRs in the also recording step, and further recording (139) the GR count (N) as a field in the trace entry (16) when the trace entry is enabled.
Claim 157
Dependent Claim
36 words
A program tracing method as defined in a preceding Claim, further comprising: executing a separate program on each CPU in an MP with independent enablement of the program tracing method in each CPU in the MP.
Claim 158
Dependent Claim
156 words
A program tracing method as defined in a preceding Claim, further comprising: the providing step also providing in the tracing-control CR one or more traceable-instruction flag fields (A, B) in addition to the trace-instruction-control flag field (E), each traceable-instruction flag field being associated with a set of one or more instructions of a predefined type which are not primarily defined to perform a tracing function during execution, the testing step (112, 113) also indicating when a traceable-instruction is being executed by the IE (23), the forming step (106, 107) also forming a trace entry by the IE when the testing step indicates an executing instruction is in a set having a traceable-instruction flag field in an enabled state, and the inserting step (108, 109) also inserting the trace entry into the trace table at a trace-entry-address in main storage obtained from the tracing-control CR of the CPU executing the forming step for an enabled traceable instruction.
Claim 159
Dependent Claim
75 words
A program tracing method as defined in Claim 9, further comprising: generating an entry identifier (ID) code corresponding to an operation code for an executing instruction associated with an enabled flag field in the tracing-control CR, the enabled flag field being either the trace-instruction-control flag field (E) or the traceable instruction flag field (A or B), the forming step (106, 107, 137) also forming the trace entry with a field containing the entry identifier code.
Claim 160
Dependent Claim
74 words
A program tracing method as defined in Claim 10, further comprising: the providing step also providing a branch-instruction flag field (B) as one of the traceable-instruction flag fields, the branch-instruction flag field enabling the tracing of a subset of branch instructions, the generating step (106) generating an entry identifier code corresponding to both the operation code for the executing instruction and an addressing mode existing if a branch is taken by the branch instruction.
Claim 161
Dependent Claim
44 words
A program tracing method as defined in Claim 10 or 11, further comprising: the providing step also providing an address-space flag field (A) as one of the traceable-instruction flag fields, the address-space flag field enabling the tracing of a subset of address space instructions.
Claim 162
Dependent Claim
196 words
A program tracing method as defined in Claims 1, 7 or 9, further comprising: storing (104, 105, 131) the state of a page-boundary bit position found in the address in the tracing-control CR after the testing step detects an executing instruction to be a trace instruction or a traceable instruction which has a corresponding flag field enabled in the CR, computing (104, 105, 133) by the IE of a length of a trace entry for the executing trace instruction, adding the length found by the computing step to the trace-entry address currently in the CR to obtain a next entry address to be put into the CR if the current entry address in the CR can be used, also storing (104, 105, 134) the state of a page-boundary bit position found in the next entry address obtained from the adding step, comparing (104, 105, 136) the states of the page-boundary bit positions obtained by the storing and also storing steps, and performing the inserting step (108, 109, 139) if the comparing step finds equality between the page-boundary bit positions, whereby the trace entry (16) being made by the inserting step will not cross a page boundary.
Claim 163
Dependent Claim
151 words
A program tracing method as defined in Claim 13, further comprising: signalling (144) a page-boundary crossing if the comparing step finds inequality between the page-boundary bit positions, nullifying (145) the execution for the instruction being executed to nullify the instruction results in response to the signalling step, interrupting (146) a program containing the instruction being executed, initiating (147) a storage allocation program to assign another page frame to the trace table, inserting an address origin of the another page frame into the tracing-control CR as the next entry address for the trace table, and restarting the execution of the nullified instruction after another page frame is assigned by the storage allocation program responding to the initiating step, whereby the next tracing entry in the trace table for the CPU is inserted at the beginning of the another page frame at the address of the trace-entry-address field in the tracing control CR.
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