EP0130380A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system
Assignee: International Business Machines Corp
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Filing: 1984-05-30
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Granted: —
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Expires: 2004-05-30
Abstract
Abstract A mechanism for performing fast and efficient full shift, merge, insert and bit alignment functions within one operating machine cycle of a host primitive instructions set computing system. In general, the circuitry performs a ring shift under control of a mask. The circuitry further combines essentially parallel rotate and mask and merge functions all executable in one machine cycle. The circuitry further allows the provision of powerful bit, digit, and bit rotate with mask instructions which are particularly useful primitive operations for decimal packing and unpacking functions as well as for implementing floating point preshifting and normalization functions.
Inventors
- 👤 Hsieh Tung Hao
- 👤 Peter Willy Markstein
- 👤 Georg Radin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 03:28
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30018; G06F9/30032; G06F9/30036; G06F9/30038; G06F9/30145; G06F9/3016; G06F9/30167
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
267 words
In a digital electronic computing system having a single machine cycle executable instruction set and including a memory hierarchy comprising a main memory and a high-speed cache, a Central Processing Unit (CPU) (12) and a bus network interconnecting same, said CPU including an arithmetic and logic unit (ALU) (42) for performing mathematical and logical operations on data supplied thereto, an instruction unit (32) operable in cooperation with a plurality of simultaneously accessible general purpose registers (30) and said ALU for processing primitive instructions to be performed by said system, and condition code generating means (50) for generating a plurality of specified condition bits in accordance with the output of the ALU and the instruction unit, characterized by, a mechanism for.performing single machine cycle executable Mask and Rotate instructions in said CPU, said mechanism including: means (62) operable substantially in parallel for; generating an N bit mask word from transition points address specified by the instruction, means (60) for rotating an N-bit subject operand which is to be partially merged with an N-bit object operand by an amount specified in said instruction, means for obtaining said N-bit object operand from data specified in said instruction, means (66) for merging said rotated subject operand into said object operand under control of said mask so that data representative of the object operand is retained where said mask has a first binary content and data representative of the rotated subject operand is retained where said mask has the opposite binary content, and means (R2) for returning said retained merged N-bit word to a register in the CPU specified by said instructions.
Claim 2
Dependent Claim
267 words
In a digital electronic computing system having a single machine cycle executable instruction set and including a memory hierarchy comprising a main memory and a high-speed cache, a Central Processing Unit (CPU) (12) and a bus network interconnecting same, said CPU including an arithmetic and logic unit (ALU) (42) for performing mathematical and logical operations on data supplied thereto, an instruction unit (32) operable in cooperation with a plurality of simultaneously accessible general purpose registers (30) and said ALU for processing primitive instructions to be performed by said system, and condition code generating means (50) for generating a plurality of specified condition bits in accordance with the output of the ALU and the instruction unit, characterized by, a mechanism for.performing single machine cycle executable Mask and Rotate instructions in said CPU, said mechanism including: means (62) operable substantially in parallel for; generating an N bit mask word from transition points address specified by the instruction, means (60) for rotating an N-bit subject operand which is to be partially merged with an N-bit object operand by an amount specified in said instruction, means for obtaining said N-bit object operand from data specified in said instruction, means (66) for merging said rotated subject operand into said object operand under control of said mask so that data representative of the object operand is retained where said mask has a first binary content and data representative of the rotated subject operand is retained where said mask has the opposite binary content, and means (R2) for returning said retained merged N-bit word to a register in the CPU specified by said instructions.
Claim 3
Dependent Claim
32 words
A mechanism for performing mask and rotate instructions as set forth in Claim 1 including means (63) for accessing all operands in said general purpose registers and in the instruction register concurrently.
Claim 4
Dependent Claim
96 words
A mechanism for performing Mask and Rotate instructions as set forth in Claim 2 wherein said means (62) for generating said N-bit mask includes means for generating a three-part mask comprising strings of 0's surrounding at least a single "1" or the inverse, said means including, means (70) for accessing a pair of transition point addresses directly specified in said instruction which specify the extent of this portion of the central portion of said Mask, and means (72, 76) for decoding each of said transition points and supplying said decoded information to Mask generating circuitry (80).
Claim 5
Dependent Claim
86 words
A mechanism for performing Mask and Rotate instructions as set forth in Claim 2 wherein said mask generating means comprises means for generating a two-part mask comprising a string of '0's followed by a string of at least a single '1's or its inverse, said means further including, means for obtaining a single transition point . address from said instruction, decoding said transition point address into an edge definition address and supplying said decoded address to a Mask Generating Logic circuit which produces the required mask.
Claim 6
Dependent Claim
79 words
A mechanism for performing Mask and Rotate instructions as set forth in Claim 2 wherein said means for obtaining the object operand includes, means for selectively accessing a specified general purpose register (20) in the CPU (12), a working register (MQ) operatively associated with said ALU, an N-bit word consisting of all '0's or an N-bit word consisting of all '1's or all '0's depending upon the condition of a sign bit stored in a specified general purpose register.
Claim 7
Dependent Claim
62 words
A mechanism for performing single-cycle Mask and Rotate instructions as set forth in Claim 5 including means (63) for accessing said General Purpose Registers (30) and the Instruction Register (32) to supply all of the instruction parameters contained in the Instruction Register and the General Purpose Registers substantially in parallel to said mask generating, subject operand rotating and object operand obtaining means.
Claim 8
Independent Claim
177 words
A method for use in a program controlled digital electronic computing system for specifying a powerful class of Mask and Rotate Instructions capable of performing a wide variety of data shifting functions, said functions including rotating an N-bit subject operand a predetermined distance and inserting a portion of same under control of an N-bit mask into a variety of different types of N-bit object operands, said method including the steps of specifying the address in local high speed storage registers of the subject operand, a portion of which is to be inserted into said object operand, specifying the transition point addresses of a Mask which defines the field of the subject operand to be inserted and also the specific address within the object operand where the subject operand is to be inserted, specifying the amount of rotation of the subject operand necessary to align a particular field thereof with the address of the object operand into which said field is to be inserted, and specifying the object operand into which said subject operand is to be inserted.
Claim 9
Independent Claim
177 words
A method for use in a program controlled digital electronic computing system for specifying a powerful class of Mask and Rotate Instructions capable of performing a wide variety of data shifting functions, said functions including rotating an N-bit subject operand a predetermined distance and inserting a portion of same under control of an N-bit mask into a variety of different types of N-bit object operands, said method including the steps of specifying the address in local high speed storage registers of the subject operand, a portion of which is to be inserted into said object operand, specifying the transition point addresses of a Mask which defines the field of the subject operand to be inserted and also the specific address within the object operand where the subject operand is to be inserted, specifying the amount of rotation of the subject operand necessary to align a particular field thereof with the address of the object operand into which said field is to be inserted, and specifying the object operand into which said subject operand is to be inserted.
Claim 10
Dependent Claim
39 words
A method for specifying mask and rotate instructions as set forth in Claim 7 including specifying an object operand which is directly obtainable from the content of the general purpose register or from the content of the instruction register.
Claim 11
Dependent Claim
38 words
A method for specifying mask and rotate instructions as set forLh in Claim 8 including prefetching all data required by said instruction in the system general purpose registers whereby no memory operations are required to perform said operation.
Claim 12
Dependent Claim
81 words
A method for specifying mask and rotate instructions as set forth in Claim 7 including performing rotate and store operations to realign a multi-word segment of data on different byte boundaries in the system memory which comprises utilizing a sequence of rotate and instructions to effect said data alignment further including; specifying as the new subject operand of a given rotate instruction the object operand of the preceding instruction, and returning the successive merged results as the appropriately rotated data string.
References Cited (Backward Citations)
No citation records indexed.
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