EP0130365A2
Expired / Lapsed
EP
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Very large scale integrated circuit fabricated from a master slice in cascode switch logic
Assignee: International Business Machines Corp
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Filing: 1984-05-28
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Granted: —
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Expires: 2004-05-28
Abstract
Abstract A very large scale integrated circuits from a master slice (1), for use in an automated placement and wiring environment is made from a semiconductor electronic quality wafer and the like, the wafer having a "brickwall" set of active elements such as bipolar or field-effect transistors together with associated passive elements arranged in a master slice image. The master slice (1) is personalized using optimization techniques including among other steps, the steps of modeling, developing and validating primitive logic diagrams, determining element placement by a Monte Carlo simulated annealing method, selecting hierarchical wiring by a maze runner algorithm and further validation.
Inventors
- 👤 James William Davis
- 👤 Frank Duane Jones
- 👤 Victor Stewart Moore
- 👤 Nandor Gyorgy Thoma
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 18:32
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1738
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
56 words
A very large scale integrated circuit fabricated from a master slice in cascode switch circuits in an automated placement and wiring environment characterized in that it comprises: a semiconductor electronic quality wafer and the like having a "brickwall" set of active elements such as Field Effect Transistors or bipolar transistors, arranged in a master slice image.
Claim 2
Dependent Claim
56 words
A very large scale integrated circuit fabricated from a master slice in cascode switch circuits in an automated placement and wiring environment characterized in that it comprises: a semiconductor electronic quality wafer and the like having a "brickwall" set of active elements such as Field Effect Transistors or bipolar transistors, arranged in a master slice image.
Claim 3
Dependent Claim
24 words
The circuit of Claim 1 further comprising: two general areas, defined on said master slice including an input/output cell perimeter and cascode logic area.
Claim 4
Dependent Claim
24 words
The circuit of Claim 1 or 2 wherein said active elements are selected for the support of a FET Cascode Current Switch circuit/logic technology.
Claim 5
Dependent Claim
79 words
The circuit of claim 1, 2 or 3 further comprising additional active Field Effect transistor elements positioned and selectively interconnected with the elements on said master slice by way of contact holes and metal wiring planes and bonding pads for connecting to logic service terminals, thereby producing a completed personalized wafer whereby said wafer may be probe tested, sectioned and sorted into good die, said good die thereafter being assembled into a package, sealed and subjected to further testing.
Claim 6
Independent Claim
94 words
A method of fabricating the circuit according to any one of claims 3 or 4, for stockpiling in a substock awaiting further steps in defining a completed functional product incorporating cascode current switch circuits, comprising the step of : (1) locating a silicon wafer and the like; (2) processing said wafer to produce an isolation region thereon; (3) processing said wafer to produce a source/drain diffusion region thereon; and (4) processing said wafer to produce a polysilicon gate region thereon, whereby the vertical structures of all the active components on the wafer is complete.
Claim 7
Dependent Claim
24 words
The circuit of claim 1 or 2 wherein said active elements are selected for the support of a differential cascode current switch logic technology.
Claim 8
Dependent Claim
78 words
The circuit of claim 1, 2 or 6 further comprising additional active and passive components positioned and selectively interconnected with the elements on said master slice by way of contact holes and metal wiring planes and bonding pads for connecting to logic service terminals, thereby producing a completed personalized wafer whereby said wafer may be probe tested, sectioned and sorted into good die, said good die thereafter being assembled into a package, sealed and subjected to further testing.
Claim 9
Independent Claim
106 words
A method of fabricating the circuit according to any one of claims 6 or 7, for stockpiling in a substock awaiting further steps in defining a completed functional product, comprising the step of : (1) locating a silicon wafer and the like ; (2) processing said wafer to produce a bottom isolation region thereon ; (3) processing said wafer to produce a collector region thereon ; (4) processing said wafer to produce a base diffusion region thereon ; and (5) processing said wafer to produce an emitter diffusion region thereon, whereby the vertical structures of all the active and passive components on the wafer is complete.
Claim 10
Dependent Claim
119 words
A method of fabricating the circuit according to claim 7 or 8, for stockpiling in a substock awaiting further steps in defining a completed functional product, comprising the steps of : (1) oxidizing and locating a silicon wafer and the like ; (2) processing said wafer to produce a buried collector region thereon ; (3) processing said wafer to produce a bottom isolation region thereon ; (4) processing said wafer to produce a collector reach through region thereon ; (5) processing said wafer to produce a base diffusion region thereon ; and (6) processing said wafer to produce an emitter diffusion region thereon, whereby the vertical structures of all the active and passive components on the wafer is complete.
Claim 11
Dependent Claim
24 words
The circuit of claim 1 or 2 wherein said active elements are selected for the support of a Differential Cascode Voltage Switch circuit/logic technology.
Claim 12
Dependent Claim
81 words
The circuit of claim 1, 2 or 10 further comprising additional active components of N and P polarity positioned and selectively interconnected with the elements on said master slice by way of contact holes and metal wiring planes and bonding pads for connecting to logic service terminals, thereby producing a completed personalized wafer whereby said wafer may be probe tested, sectioned and sorted into good die, said good die thereafter being assembled into a package, sealed and subjected to further testing.
Claim 13
Dependent Claim
80 words
A method of fabricating the circuit according to claim 10 or 11, for stockpiling in a substock awaiting further steps in defining a completed functional product, comprising the steps of : (1) locating a semiconductor electronic quality wafer and the like ; ' (2) processing said wafer in a CMOS sequence having two orthogonal wiring plane capability to produce a master slice having a plurality of active FET elements thereon of both N and P polarity on the same wafer.
Claim 14
Dependent Claim
94 words
A method of fabricating the circuit according to claim 10 or 11, for stockpiling in a substock awaiting further steps in defining a completed functional product, comprising the steps of : (1) oxidizing and locating a silicon wafer and the like ; (2) processing said silicon wafer in a CMOS sequence having two orthogonal wiring plane capability to produce a master slice having a plurality of active FET elements thereon of both N and P polarity on the same wafer whereby the vertical structures of all the active elements on the wafer is complete.
Claim 15
Independent Claim
90 words
The method according to any one of claims 5, 8, 9, 12 or 13 further comprising the following steps of personalization : (1) opening contact holes for said active and passive components; (2) selectively interconnecting said elements with metal wiring planes; (3) connecting to logic terminals thereon to thereby produce a completed personalized wafer; (4) probe testing the completed personalized wafer; (5) sectioning said wafer into die; (6) sorting out good die; (7) assembling each sorted good die into a package; and (8) processing said packages through a final test
Claim 16
Dependent Claim
169 words
A cascode logic design methodology for producing cascode switch products optimizing high level structure and primitive implementation comprising the steps of: (1) modeling, simulating and optimizing the high level structures utilizing generic descriptions such as logic maps and truth tables of various machine functional partitions; (2) decomposing said generic description into a primitive logic form such as tree networks. (3) producing primitive logic machine diagrams updated with various logic groups and longest path delays; (4) interrogating said machine diagrams in order to generate clocks; (5) validating the primitive logic by comparison with the logic model functional patterns from which they were derived; (6) reviewing the primitive level implementation for further optimization of design; (7) determining hierarchical placement by utilizing a Monte Carlo simulated annealing method for discrete optimization; (8) selecting hierarchical wiring by means of a maze runner algorithm; (9) proceeding with physical validation rules and test pattern generation; (10) producing microelectronic Field Effect transistor circuits by masking and fabrication; and (11) testing and performing logic model hardware validation.
Claim 17
Dependent Claim
169 words
A cascode logic design methodology for producing cascode switch products optimizing high level structure and primitive implementation comprising the steps of: (1) modeling, simulating and optimizing the high level structures utilizing generic descriptions such as logic maps and truth tables of various machine functional partitions; (2) decomposing said generic description into a primitive logic form such as tree networks. (3) producing primitive logic machine diagrams updated with various logic groups and longest path delays; (4) interrogating said machine diagrams in order to generate clocks; (5) validating the primitive logic by comparison with the logic model functional patterns from which they were derived; (6) reviewing the primitive level implementation for further optimization of design; (7) determining hierarchical placement by utilizing a Monte Carlo simulated annealing method for discrete optimization; (8) selecting hierarchical wiring by means of a maze runner algorithm; (9) proceeding with physical validation rules and test pattern generation; (10) producing microelectronic Field Effect transistor circuits by masking and fabrication; and (11) testing and performing logic model hardware validation.
References Cited (Backward Citations)
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