EP0130103A1
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EP
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Charge-coupled device image sensor and method for asynchronous readout
Assignee: Fairchild Semiconductor Corp
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Filing: 1984-06-06
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Granted: —
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Expires: 2004-06-06
Abstract
Abstract A CCD image sensor and method for asynchronous readout without combining charge packets. A plurality of photoelements (PE) is associated with a plurality of sequentially connected CCD storage elements (CCD). Each CCD element is connected to receive and store the electrical charge produced by an associated photoelement as a charge packet. Charge packets are shifted out of the CCD elements by selectively transferring the charge packet from the first in the sequentially connected CCD storage elements during a first time period to empty the first storage element without effecting a transfer from any other CCD storage element and thereafter transferring charge packets only to an empty CCD storage element in the sequence of CCD storage elements, thereby avoiding the combining of charge packets during the transfer. The asynchronous transfer technique is applicable to both CCD linear and area image sensors and permits the use of CCD serial shift registers (20) having CCD storage elements in substantially equal in number to the number of photoelements, avoiding the usual requirement of CCD storage elements numbering twice the number of photoelements.
Inventors
- 👤 Yum Tom Chan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 05:04
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/15; H10F39/152; H04; H04N; H04N25/00; H04N25/70; H04N25/71; H04N25/745; H04N25/73; H10F39/153
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
133 words
A CCD image sensor comprising: a plurality of photoelements [PE(l,l), PE(l,n)] each producing a packet of electrical charges related in magnitude to the intensity of light incident thereon; a plurality of sequentially connected CCD storage elements [CCD(l,l), CCD(l,n)] each connected to receive and store the electrical charge produced by an associated photoelement as a charge packet, characterized by comprising: means (26, 28) for selectively transferring the charge packet from the first [CCD(1,1)] in the sequentially connected CCD storage elements during a first time period to empty the first storage element [CCD(1,1)] without effecting a transfer from any other CCD storage element and thereafter transferring charge packets only to an empty CCD storage element in the sequence of CCD storage elements [CCD(l,l), CCD (l,n)], thereby avoiding the combining of charge packets during the transfer.
Claim 2
Dependent Claim
133 words
A CCD image sensor comprising: a plurality of photoelements [PE(l,l), PE(l,n)] each producing a packet of electrical charges related in magnitude to the intensity of light incident thereon; a plurality of sequentially connected CCD storage elements [CCD(l,l), CCD(l,n)] each connected to receive and store the electrical charge produced by an associated photoelement as a charge packet, characterized by comprising: means (26, 28) for selectively transferring the charge packet from the first [CCD(1,1)] in the sequentially connected CCD storage elements during a first time period to empty the first storage element [CCD(1,1)] without effecting a transfer from any other CCD storage element and thereafter transferring charge packets only to an empty CCD storage element in the sequence of CCD storage elements [CCD(l,l), CCD (l,n)], thereby avoiding the combining of charge packets during the transfer.
Claim 3
Dependent Claim
24 words
The CCD image sensor of claim 1 characterized in that said photoelements [PE(l,l), PE(l,n)] are arranged linearly to form a CCD linear image sensor.
Claim 4
Dependent Claim
61 words
The CCD image sensor of claim 1 characterized in that said photoelements are arranged in a plurality of horizontal rows [PE(l,l), PE(m,l)] and vertical columns [PE(l,l), PE(l,n)], and including a plurality of sequentially connected CCD storage elements associated with each column of photoelements and forming a vertical transport shift register for the associated column, thereby forming a CCD area image sensor.
Claim 5
Dependent Claim
45 words
The CCD image sensor of any one of claims 1 to 3 characterized by further comprising an additional CCD storage element [CCD(1,0)] connected to the first of said sequentially connected CCD storage elements to receive the charge packet transferred from said first CCD storage element.
Claim 6
Dependent Claim
50 words
The CCD image sensor of any one of claims 1 to 4 characterized in that said selective transferring means comprises transfer control means (26) for controlling the transfer of charge packets from each CCD storage element, and means (28) for successively enabling each transfer control means during successive transfer periods.
Claim 7
Dependent Claim
50 words
The CCD image sensor of claim 5 characterized in that said successive enabling means (28) comprises a multi-stage binary shift register connected to said transfer control means (26), and means for successively loading a predetermined binary signal level into each stage of the shift register during each successive transfer period.
Claim 8
Independent Claim
165 words
A method for shifting a plurality of charge packets stored in a CCD serial shift register (20-1) to the output of the serial shift register, the charge packets being initially stored in a plurality of sequential stages [CCD(l,l), CCD(l,n)] of the shift register without intermediate empty stages, the method characterized by comprising the steps of: starting with the first charge packet which is in the shift register stage [CCD(1,1)] nearest the output of the shift register, shifting the charge packet in each of the plurality of serial shift register stages [CCD(l,l), CCD(l,n)] from its initial storage stage into an immediately successive storage stage only after the charge packet in the immediately successive storage stage has been shifted; and, after a charge packet has been shifted from its initial storage stage into the immediately successive storage stage, shifting said previously shifted charge packet each time any other charge packet is shifted until each stored charge packet is shifted to the output of the serial shift register.
Claim 9
Independent Claim
165 words
A method for shifting a plurality of charge packets stored in a CCD serial shift register (20-1) to the output of the serial shift register, the charge packets being initially stored in a plurality of sequential stages [CCD(l,l), CCD(l,n)] of the shift register without intermediate empty stages, the method characterized by comprising the steps of: starting with the first charge packet which is in the shift register stage [CCD(1,1)] nearest the output of the shift register, shifting the charge packet in each of the plurality of serial shift register stages [CCD(l,l), CCD(l,n)] from its initial storage stage into an immediately successive storage stage only after the charge packet in the immediately successive storage stage has been shifted; and, after a charge packet has been shifted from its initial storage stage into the immediately successive storage stage, shifting said previously shifted charge packet each time any other charge packet is shifted until each stored charge packet is shifted to the output of the serial shift register.
Claim 10
Dependent Claim
63 words
The method of claim 7 characterized in that the charge packets are shifted from their initial storage stages to the immediately successive stages of the shift registers asynchronously by successively enabling the clocking of the shift register stages such that a charge packet can only be shifted to the immediately successive storage stage after the shifting of immediately successive stage has been enabled.
Claim 11
Dependent Claim
39 words
The method of claim 8 characterized in that the clocking of the shift register stages is accomplished by a two-phase clock signal (φV1, ØV2) and the enabling step comprises enabling the clocking of successive pairs of shift register stages.
Claim 12
Dependent Claim
163 words
The method of claim 9 characterized in that the step of shifting the charge packets asynchronously comprises: (a) enabling the clocking of a pair of first and second shift register stages [CCD(1,2), CCD(1,3)] the second stage being further from the output than the first stage; (b) applying the two-phase clock signal (φV1, ØV2) to the enabled pair of shift register stages to first shift the charge packet from the second stage into the first stage of the enabled pair of stages and then shift the charge packet from the first stage of an adjacent pair of stages into the second stage of said enabled pair after said second stage has been emptied and while shifting the charge packet out of the first stage of the enabled pair; (c) maintaining the pair of first and second shift register stages enabled; and (d) repeating steps (a) through (c) for each adjacent pair of shift register stages until all shift register are enabled to be clocked.
References Cited (Backward Citations)
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