Logic and amplifier cells

Claim 2

A high-speed circuit characterised by: a first device (Q1) including a high-speed transistor having an input region, an output region and a control region, said first device having a high gain bandwidth product; biasing means (Z2) connected to said control region for controlling the operating point of said first device in a mode whereby Miller-effect capacitance is minimized; a second device (Q2) including a unipolar transistor having a gate, a source and a drain, said second device having a high gain-bandwidth product, said drain connected to the input region of said first device, said gate adapted to receive an input signal for controlling the drain current and thereby the current supplied to the input region of said first device whereby the output signal from the output region of said first device is controlled at high speed.

Claim 3

The high-speed circuit of claim 1 wherein said first device is a bipolar transistor and said input region is the emitter, said output region is the collector and said control region is the base and wherein said biasing means connects said first device in a common-base mode.

Claim 4

The high-speed circuit of claim 1 wherein said first device is a unipolar transistor and said input region is the source, said output region is the drain and said control region is the gate and wherein said biasing means connects said first device in a common-gate mode.

Claim 5

The circuit of claim 1 wherein said biasing means drives said first device "on" when said second deivce is "on" and drives said first device "off" when said second device is "off".

Claim 6

The circuit of claim 4 wherein said biasing means drives said first device into saturation when "on".

Claim 7

The circuit of claim 4 wherein said biasing means includes a first element (14) having a first impedance connected between said output region and a reference voltage level and including a second element (15) having a second impedance connected between said reference voltage and said control region and where said second impedance is much less than said first impedance.

Claim 8

The circuit of claim 1 wherein said first device and said second device each have a gain-bandwidth product greater than 8 GHz.

Claim 9

The circuit of claim 3 wherein said baising means maintains said first device in the linear region whereby said output signal is a linear amplification of the input signal.

Claim 10

The circuit of claim 1 wherein said biasing means includes first RLC circuit components (Rl,Ll,Cl) connected between a first reference voltage level and said output region and includes second circuit components (R2,R3) connected between said output region and said control region to bias said first device in the linear region.

Claim 11

The circuit of claim 9 including LC circuit components (L2,C2) connected to said output region to provide said output signal.

Claim 12

The circuit of claim 9 including RC circuit components (R4,C3) connected between said source and a second reference voltage level.

Claim 13

The circuit of claim 1 wherein said first device includes a plurality of high-speed transistors (Q1-1,Q1-2) each having an input region, an output region and a control region, each of said high-speed transistors having a high gain-bandwidth product, and said first device including means (Q6) for connecting the input regions in common and including means for connecting the output regions in common and means for connecting the input regions in common whereby said high-speed transistors operate in parallel to provide said output signal, and wherein said second device includes a plurality of unipolar transistors (Q2-1...Q2-4) each having a gate, a source and a drain and each having a high gain-bandwidth product, said second device having means (R4) for connecting said sources in common, having means (R7) for connecting said drains in common, and having means (16) for connecting said gates in common to receive said input signal.

Claim 14

The circuit of claim 12 wherein said biasing means includes first RLC circuit components (R1,L1,C1) connected between a first reference voltage level and said output region and includes second circuit components (R2,R3) connected between said output region and said control region to bias said first device in the linear region.

Claim 15

The circuit of claim 13 including LC circuit components (L2,C4) connected to said output region to provide said output signal.

Claim 16

The circuit of claim 14 inlcuding RC circuit components (R4,C2) connected between said source and a second reference voltage level.

Claim 17

The circuit of claim 13 including RLC circuit components (R8,L2,C4) including an output resistor connected to said output regions of said high-speed transistors to provide said output signal whereby high voltage spikes in an output load are suppressed by said output resistor.

Claim 18

The circuit of claim 12 wherein the transistors in said first device and in said second device each have a gain-bandwidth product greater than 2 GHz.

Claim 19

The circuit of claim 6 wherein said first element is a transistor and wherein said second element is a transistor.

Claim 20

The circuit of claim 1 wherein the first device is a power transistor for driving a load having resonant circuits including a first resonant circuit having total inductant L and a trace capacitor C T and including a second resonant circuit having said inductant L and retrace capacitance C R and wherein said high-speed circuit synchronizes the operation of said resonant circuits.

Claim 21

The circuit of claim 16 wherein said biasing means includes a field-effect device connected to drive said control region, said field-effect device connected to receive said input signal.

Claim 22

A high-speed power circuit for driving a load having resonant circuits characterised by: a first device (Q1) including a high-speed power transistor having an input region, an output region and a control region; baising means (Z2) connected to said control region for controlling the operating point of said first device in a mode whereby Miller-effect capacitance is minimized; a second device (Q2) including a unipolar transistor having a gate, a source and a drain, said drain connected to the input region of said first device, said gate adapted to receive an input signal for controlling the drain current and thereby the current supplied to the input region of said first device whereby the output signal from the output region of said first device is controlled at high speed; said output signal connected to synchronize said resonant circuit in said load.

Claim 23

A high-speed power circuit for driving a load having resonant circuits characterised by: a first device (Q1) including a high-speed power transistor having an input region, an output region and a control region; baising means (Z2) connected to said control region for controlling the operating point of said first device in a mode whereby Miller-effect capacitance is minimized; a second device (Q2) including a unipolar transistor having a gate, a source and a drain, said drain connected to the input region of said first device, said gate adapted to receive an input signal for controlling the drain current and thereby the current supplied to the input region of said first device whereby the output signal from the output region of said first device is controlled at high speed; said output signal connected to synchronize said resonant circuit in said load.