EP0129651A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Dynamic semiconductor memory having sensing amplifiers
Assignee: Toshiba Corp
•
Filing: 1984-04-09
•
Granted: —
•
Expires: 2004-04-09
Abstract
Abstract A large capacity and high speed semiconductor memory is disclosed. Static memory cell rows are provided so as to correspond to dynamic memory cell rows in a dynamic memory cell array. Information is transferred with transfer means (51,52) between static memory cells (600) in the static memory cell rows and dynamic memory cells (400) corresponding thereto. Access for a read/write operation externally required is effected to static memory cell rows.
Inventors
- 👤 Yukimasa Uchida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 23:23
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/106; G11C11/00; G11C11/005; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C7/1078; G11C7/1087
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
148 words
A semiconductor memory comprising a dynamic memory cell array wherein dynamic memory cells (400) for storing information therein are arranged in the row and column directions in a matrix manner, word lines (111,112) commonly connected in the row direction to said dynamic memory cells (400) in said dynamic memory cell array, bit lines (B,B) commonly connected in the column direction to said dynamic memory cells in said dynamic memory cell array, and a sense amplifier row having sense amplifiers (20) for sense-amplifying a potential difference between paired bit lines, characterised by: (a) a static memory cell row having static memory cells (600) corresponding to said dynamic memory cells (400) located in the row direction in said dynamic memory cell array; and (b) transfer gate means (51,52) for transferring information between said static memory cells (600) in said static memory cell row and the corresponding dynamic memory cells (400).
Claim 2
Dependent Claim
148 words
A semiconductor memory comprising a dynamic memory cell array wherein dynamic memory cells (400) for storing information therein are arranged in the row and column directions in a matrix manner, word lines (111,112) commonly connected in the row direction to said dynamic memory cells (400) in said dynamic memory cell array, bit lines (B,B) commonly connected in the column direction to said dynamic memory cells in said dynamic memory cell array, and a sense amplifier row having sense amplifiers (20) for sense-amplifying a potential difference between paired bit lines, characterised by: (a) a static memory cell row having static memory cells (600) corresponding to said dynamic memory cells (400) located in the row direction in said dynamic memory cell array; and (b) transfer gate means (51,52) for transferring information between said static memory cells (600) in said static memory cell row and the corresponding dynamic memory cells (400).
Claim 3
Dependent Claim
170 words
A semiconductor memory according to claim 1 characterised by row selection means (110) for selecting a word line (111,112) of dynamic memory cell row of a desired row address in said dynamic memory cell array, and column selection means (90) for selecting static memory cell (600) of a desired column address in said static memory cell row, thereby transferring the information of said dynamic memory cell row commonly connected to word line selected by said row selection means (110) to said static memory cell row with said transfer gate means (51,52), effecting a read/write operation with respect to the static memory cell (600) of a desired column address through a data line connected by said column selection means, transferring the information of said static memory cell row, to which said read/write operation has been effected, to said dynamic memory cell row commonly connected to the word line selected by said row selection means (110) with said transfer gate means (51,52), and rewriting the information to said dynamic memory cell row.
Claim 4
Dependent Claim
66 words
A semiconductor memory according to claim 2 characterised in that said row selection means (110) comprises a refresh-counter (170) producing internal row address signals for a self-refresh which is counted up every a predetermined time period, thereby self-refreshing the information of the dynamic memory cell row corresponding to row address designated by internal row address signals produced from said refresh counter with said sense amplifier row.
Claim 5
Dependent Claim
50 words
A semiconductor memory according to claim 3 characterised in that a read/write operation to said static memory cells (600) during the refresh operation of said dynamic memory cells (400) is enabled by interrupting said static memory cells (600) and said dynamic memory cells (400) with said transfer gate means (51,52).
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.