EP0129432A2
Expired / Lapsed
EP
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Digital processor
Assignee: 542435 Ontario Ltd Dba Syntronics
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Filing: 1984-06-18
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Granted: —
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Expires: 2004-06-18
Abstract
Abstract A processorforgenerating digital data organized as samples in successive time slots of a time division multiplexed multi-channel signal, as in the digital synthesis of complex waveforms, uses a sample generator (4) configured to allow parallel operations under control of micro-programs limited in length so that they can be executed within a single time slot. The sample generator draws data from a number of registers (f, g, h, i, j,r, v, z), some of which (r, y, z) receive data preprocessed in an interpolator (3) during the preceding time slot. Variable parameter data is supplied to the sample generator and interpolator, with data supplied to the former appropriately delayed, from a cyclically addressed memory array comprising two memories (a, b) of which one is always available for the reading of data whilst the other is being updated from an external source.
Inventors
- 👤 Ronald G. Everett
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 03:54
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0321
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
224 words
A processor for generating digital data arranged as samples in successive time slots of a time division multiplexed multiple channel signal, characterized in that it comprises a sample generator (4) having a plurality of data registers (f, g, h, i, j, r, v, y, z, cc), a plurality of data buses (A, B, F, S, X, Y), a plurality of interbus registers (k, 1, m, n, o, p, q, s, t, u, w, x, aa, bb), and at least one arithmetic element (14, 15), the inputs and outputs of the interbus registers, the outputs of the data registers, and the function of the at least one arithmetic element all being selectively enabled by control signals, and the interconnection of the registers, buses and element being such that selective simultaneous enabling of these components permits simultaneous execution of plural different operations in different parts of the processor, a microprogram memory (d) configured to store microprograms of defined maximum length, and a decoder (20) connected to receive successive digital words representing steps in a selected microprogram from the microprogram memory and to decode said words into selected ones of said control signals, the defined maximum length of the micro- programs'beingsuch that the sum of the time required to execute the steps of a microprogram does not exceed the length of a time slot of said signal.
Claim 2
Dependent Claim
224 words
A processor for generating digital data arranged as samples in successive time slots of a time division multiplexed multiple channel signal, characterized in that it comprises a sample generator (4) having a plurality of data registers (f, g, h, i, j, r, v, y, z, cc), a plurality of data buses (A, B, F, S, X, Y), a plurality of interbus registers (k, 1, m, n, o, p, q, s, t, u, w, x, aa, bb), and at least one arithmetic element (14, 15), the inputs and outputs of the interbus registers, the outputs of the data registers, and the function of the at least one arithmetic element all being selectively enabled by control signals, and the interconnection of the registers, buses and element being such that selective simultaneous enabling of these components permits simultaneous execution of plural different operations in different parts of the processor, a microprogram memory (d) configured to store microprograms of defined maximum length, and a decoder (20) connected to receive successive digital words representing steps in a selected microprogram from the microprogram memory and to decode said words into selected ones of said control signals, the defined maximum length of the micro- programs'beingsuch that the sum of the time required to execute the steps of a microprogram does not exceed the length of a time slot of said signal.
Claim 3
Dependent Claim
28 words
A processor according to Claim 1, characterized by incorporating arithmetic elements in the form of at least one multiplier (14) and at least one arithmetic logic unit (15).
Claim 4
Dependent Claim
80 words
A processor according to Claim 1, characterized in that the sample generator (4) is associated with at least one interpolator (3) for preprocessing data and outputting that data to certain of the data registers (r, y, z), the interpolator operating synchronously with the sample generator to preprocess in one time slot data utilized by the sample generator in the next time slot, and to deliver said processed data to said data registers (r, y, z) associated with the sample generator.
Claim 5
Dependent Claim
52 words
A processor according to Claim 3, characterized in that the interpolator (3) is associated with data registers (17, 18) and comprises an arithmetic logic unit (ALU) configured to receive data from the data registers, as values of variables and increments of those variables, and to calculate modulated or modified values those variables.
Claim 6
Dependent Claim
162 words
A processor according to Claim 3, characterized in that it includes a memory array (a, b) storing data as to the variable parameters, means (2) cyclically to address the memory array so as successively synchronously to read out data required for generation of samples in successive time slots of the output signal, and a set of registers (f, g, h, i j, v, 17, 18) connected to receive data read from the memory array and required for the generation of a particular sample, certain of said sets of registers (f, g, h, i, j, v) being data registers associated with the sample generator, and certain of said registers (17, 18) being data registers associated with the interpolator, the data registers (f, g, h, i, j, v) associated with the sample generator being such as to delay the availablility of the data to a later time slot compared with the availability of data from the data registers (17, 18) associated with the interpolator.
Claim 7
Dependent Claim
119 words
A processor according to Claim 5, characterized in that the memory array includes a pair of memories (a, b) of which the one (b) is always synchronously addressable by the cyclical addressing means, the other memory (a) being synchronously addressable during a read phase by the cyclical addressing means, and asynchronously addressable by an externally connectable address bus (SA) during a write phase to provide data to an external data bus (SD), the one memory providing a write phase for writing data read from the other memory whilst the latter is in its read phase, and a read phase whilst the latter is in a write phase, whereby one memory is always available for the cyclical reading of data.
Claim 8
Dependent Claim
75 words
A processor according to Claim 6, characterized in that the memory array includes a data buffer system (D3, D4, D5, D6) such that one memory unit (b) may receive data during a write phase either from the other memory or from within the processor, and the other memory unit (a) may read or write data during a read or write phase from or to either the external data bus (SD) or the one memory (b).
References Cited (Backward Citations)
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