Timing signal generator

Claim 2

Circuitry for providing timing signals spaced in time by a varying amount, said circuitry comprising, calculating means for repetitively performing a calculation to repetitively provide calculation signals the value (SUM) of which varies as a function of the number of times said calculation has been repeated, and timing signal generating means for receiving said calculation signals and providing a series of timing signals spaced in time by varying amounts, one said timing signal being generated each time said value (SUM) has changed by a set amount (ACC).

Claim 3

The circuitry of claim 1 wherein said circuitry comprises a programmable digital computer and program, and wherein said calculating means and said timing signal generating means are implemented as steps of said program.

Claim 4

The circuitry of claim 1 wherein said calculating means repetitively provides calculation signals the value (SUM) of which varies quadratically with respect to the number of times said calculation has been repeated.

Claim 5

The circuitry of claim 3 wherein said calculating means provides said calculation signals spaced in time by equal amounts.

Claim 6

The circuitry of claim 4 wherein said timing signal generating means includes means to compare SUM with a comparison value, and comparison adjustment means to adjust said comparison value each time a timing signal is generated.

Claim 7

The circuitry of claim 5 wherein said comparison adjustment means includes means to decrease SUM by said set amount ACC.

Claim 8

The circuitry of claim 5 wherein said comparison adjustment means includes means to set said comparison value to the product of ACC and NSTEPS, where NSTEPS is the number of timing signals that have been generated, and ACC is a constant.

Claim 9

The circuitry of claim 4 wherein said calculating means includes count adjustment means to adjust the value N of a count signal each time a said computation signal has been provided so that SUM varies quadratically with respect to N.

Claim 10

The circuitry of claim 8 wherein said count adjustment means includes means to increase N each time a said calculation signal is provided, whereby the value SUM increases with each repetitive calculation, and the period between said timing signals decreases with time.

Claim 11

The circuitry of claim 8 wherein said count adjustment means includes means to decrease N each time a said calculation signal is provided, whereby the value SUM decreases with each repetitive calculation, and the period between said timing signals increases with time.

Claim 12

The circuitry of claim 3 wherein said calculating means includes count adjustment means to adjust the value N of a count signal each time a said calculation signal has been provided, wherein SUM varies quadratically with respect to N, and wherein said count adjustment means includes means to selectively increase N each time a said calculation signal is provided or decrease N each time a said calculation signal is provided or cause N to remain the same each time a said calculation signal is provided, whereby the period between said timing signals respectively decreases, increases or remains the same with respect to time.

Claim 13

The circuitry of claim 11 wherein said timing signal generating means includes acceleration/ deceleration means to selectively adjust said count adjustment means in response to the number of timing signals that have been provided.

Claim 14

The circuitry of 11 wherein said apparatus is used to provide timing signals for a stepper motor to operate a given number of steps by accelerating at a constant rate to a fixed speed, by operating at said fixed speed .and by decelerating at a constant rate so that said given number of steps is reached as the deceleration is completed, and wherein said count adjustment means increases N each time a calculation signal is provided until N reaches a value corresponding to said fixed speed, and wherein said acceleration/ deceleration adjustment means provides a signal indicating how many steps were required to reach said fixed speed, and said count adjustment means maintains N at that value until the number of steps remaining to reach said given number of steps equals the number required to reach said fixed speed, at which time N is decreased each time a said calculation signal is provided.

Claim 15

The circuitry of 11 wherein said apparatus is used to provide timing signals for a stepper motor to operate a given number of steps by accelerating at a constant rate to a fixed speed, by operating at said fixed speed .and by decelerating at a constant rate so that said given number of steps is reached as the deceleration is completed, and wherein said count adjustment means increases N each time a calculation signal is provided until N reaches a value corresponding to said fixed speed, and wherein said acceleration/ deceleration adjustment means provides a signal indicating how many steps were required to reach said fixed speed, and said count adjustment means maintains N at that value until the number of steps remaining to reach said given number of steps equals the number required to reach said fixed speed, at which time N is decreased each time a said calculation signal is provided.

Claim 16

The circuitry of claim 8 wherein said repetitive calculation is repetitively adding N + N + l.

Claim 17

The circuitry of claim 8 wherein said repetitive calculation is repetitively adding N.

Claim 18

The combination of the circuitry of claim 1 and apparatus capable of being driven by said timing signals.

Claim 19

The combination of claim 14 wherein said apparatus is a stepper motor that rotates a given angle in response to each said timing signal.