EP0128751A2
Expired / Lapsed
EP
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Manufacturing method of Schottky gate FET
Assignee: Toshiba Corp
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Filing: 1984-06-07
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Granted: —
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Expires: 2004-06-07
Abstract
Abstract An etched Si0 2 film component (14-3) serving as a mask at the time of formation of source and drain electrodes (26) in a surface layer of a GaAs substrate (101 by means of ion implantation is side-etched before a gate electrode (34) is formed. An Si0 2 film component (14-3) has a narrowed width smaller than a distance between the source and drain electrodes (26) while the SiO 2 film component (14-3) supports a metal mask patterned film (20) at its top surface. The Si0 2 film component (14-3) is replaced with a metal layer (34) serving as a gate of a self-aligned Schottky gate FET. According to this method, a metal with high heat resistance need not be used as a metal material of the gate layer (34).
Inventors
- 👤 Toshiyuki C/O Patent Division Terada
- 👤 Nobuyuki C/O Patent Division Toyoda
- 👤 Akimichi C/O Patent Division Hojo
- 👤 Kiyoho C/O Patent Division Kamei
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 21:23
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0614; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6738; H10D30/674; H10D30/675; H10D30/80; H10D30/87; H10D64/00; H10D64/60; H10D64/64; H10D62/00; H10D62/80; H10D62/85
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
237 words
A method of manufacturing a Schottky gate type field effect transistor, wherein an insulating layer (14, 52, 64) is formed on a compound semiconductive substrate (10, 60) and etched to obtain an insulating layer component (14-2, 52-1, 64-2) having a first width (Ll) so as to define a prospective gate electrode formation region, characterized in that said method comprises the steps of: implanting ions into said substrate (10, 60) to form in said compound semiconductor substrate (10, 60) first and second semiconductor regions (25a, 25b; 71a, 71b) corresponding to the source and drain electrodes of the transistor, said first and second semiconductor regions (25a, 25b; 71a, 71b) being self-aligned with said insulating layer component (14-2, 52-1, 64-2); side-etching said insulating layer component (14-2, 52-1, 64-2) so that said insulating layer component (14-3, 52-2, 64-4) has a second width (L2) smaller than the first width (L1); annealing said compound semiconductor substrate (10, 60); and replacing said insulating layer component (14-3, 52-2, 64-4) having the second width (12) with a metal layer (34, 44, 86) corresponding to the gate electrode, whereby a width of the gate electrode (34, 44, 86) thus obtained is smaller than a distance between the source and drain electrodes (26a, 26b; 72a, 72b) so as to decrease capacitances between the gate electrode (34, 44, 86) and the source electrode (26a, 72a) and between the gate electrode (34, 44, 86) and the drain electrode (26b, 72b).
Claim 2
Independent Claim
237 words
A method of manufacturing a Schottky gate type field effect transistor, wherein an insulating layer (14, 52, 64) is formed on a compound semiconductive substrate (10, 60) and etched to obtain an insulating layer component (14-2, 52-1, 64-2) having a first width (Ll) so as to define a prospective gate electrode formation region, characterized in that said method comprises the steps of: implanting ions into said substrate (10, 60) to form in said compound semiconductor substrate (10, 60) first and second semiconductor regions (25a, 25b; 71a, 71b) corresponding to the source and drain electrodes of the transistor, said first and second semiconductor regions (25a, 25b; 71a, 71b) being self-aligned with said insulating layer component (14-2, 52-1, 64-2); side-etching said insulating layer component (14-2, 52-1, 64-2) so that said insulating layer component (14-3, 52-2, 64-4) has a second width (L2) smaller than the first width (L1); annealing said compound semiconductor substrate (10, 60); and replacing said insulating layer component (14-3, 52-2, 64-4) having the second width (12) with a metal layer (34, 44, 86) corresponding to the gate electrode, whereby a width of the gate electrode (34, 44, 86) thus obtained is smaller than a distance between the source and drain electrodes (26a, 26b; 72a, 72b) so as to decrease capacitances between the gate electrode (34, 44, 86) and the source electrode (26a, 72a) and between the gate electrode (34, 44, 86) and the drain electrode (26b, 72b).
Claim 3
Dependent Claim
155 words
The method according to claim 1, characterized in that the step of replacing said insulating layer component (14 - 3, 64-4) with the gate electrode (34, 86) comprises substeps of: forming an organic layer (28', 74) on a structure (10, 60) characterized in that said insulating layer component (14-3, 64-4) having the second width (L2) is formed on said compound semiconductor substrate (10, 60) in such a manner that a top surface of said insulating layer component (14-3, 64-4) is exposed; removing said insulating layer component (14-3, 64-4), whereby said organic layer (28', 74) has an opening (30, 84) which has substantially the same size as the second width (L2) of said insulating layer component (14-3, 64-4), said compound semiconductor substrate (10, 60) being partially exposed through said opening (30, 84); and forming the metal layer (34, 86) on an exposed surface portion of said compound semiconductor substrate (10, 60) through said opening (30, 84).
Claim 4
Dependent Claim
43 words
The method according to claim 2, characterized in that said insulating layer component (14-2, 64-2) having the first width (L1) is etched by chemical dry etching at both side wall surfaces thereof by a given distance (AL) only substantially along a lateral direction.
Claim 5
Dependent Claim
89 words
The method according to claim 3, characterized by further comprising the step of forming a mask layer (20, 66) defining the prospective gate electrode formation region of said compound semiconductor substrate (10, 60), said mask layer (20, 66) being formed on said insulating layer (14, 52) formed on said compound semiconductor substrate (10, 60), whereby a portion of said insulating layer (14, 52) which is present under said mask layer (20, 66) is left as said insulating layer component (14-2, 64-2) obtained by etching said insulating layer (14, 52).
Claim 6
Dependent Claim
43 words
The method according to claim 4, characterized in that said mask layer (20, 66) is left on said insulating layer component (14-2, 64-2) through ion-implanting for forming the source and drain electrodes (25, 71) and side-etching of said insulating layer component (14-2, 64-2).
Claim 7
Dependent Claim
30 words
The method according to claim 5, characterized in that said mask layer (20, 66) is removed from said insulating layer component (14-3, 64-4) before said substrate (10, 60) is annealed.
Claim 8
Dependent Claim
17 words
The method according to claim 6, characterized in that said mask layer (20) comprises a metal material.
Claim 9
Dependent Claim
17 words
The method according to claim 6, characterized in that said mask layer (66) comprises a photoresist material.
Claim 10
Dependent Claim
57 words
The method according to claim 6, further comprising the step of forming in said compound semiconductor substrate (10, 60) an electrically active layer (12, 62) on which said insulating layer component (14-2, 64-2) with said mask layer (20, 66) is positioned, before said insulating layer (14, 52, 64) is formed on said compound semiconductor substrate (10, 60).
Claim 11
Dependent Claim
120 words
The method according to claim 6, characterized in that the step of forming on said compound semiconductor substrate (10) said organic layer (28') such that said top surface of said insulating layer component (14-3) is exposed, comprises the substeps of: applying an organic material (28) on an entire surface of said compound semiconductor substrate (10) having the source and drain electrodes (26a, 26b) and said insulating layer component (14-3) of the second width (L2), said organic material including a photoresist material; and etching a surface portion of a photoresist layer (28) of the organic material by anisotropic etching, thereby decreasing a thickness of said photoresist layer (28) so as to expose said top surface of said insulating layer component (14-3).
Claim 12
Dependent Claim
118 words
The method according to claim 6, characterized in that the step of forming on said compound semiconductor substrate (60) said photoresist layer (74) such that said top surface of said insulating layer component (64-4) is exposed, comprises the substeps of: applying an organic material (74) on an entire surface of said compound semiconductor substrate (60) having the source and drain electrodes (72a, 72b) and said insulating layer component (64-4) of the second width, said organic material including a photoresist material; and partially recessing a portion of a photoresist layer (74) of the organic material and performing anisotropic etching to expose the top surface of said insulating layer component (64-4) through a bottom surface of a recessed portion (82).
References Cited (Backward Citations)
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