← Back to Patent Explorer
EP0127020A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method of manufacturing multi-layer semiconductor device

Assignee: Toshiba Corp
•
Filing: 1984-05-07
•
Granted: —
•
Expires: 2004-05-07
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of manufacturing a semiconductor device is disclosed. In the manufacturing method, an impurity diffusion layer (22) as a first interconnection layer is formed on a semiconductor substrate (21). Then, an aluminum layer (24) as a second interconnection layer is formed on the semiconductor substrate (21) through an insulating film (23) interposing therebetween. Another insulating layer (25) is further formed on the aluminum layer (24). An anisotropic etching process is applied to the Insulating layer (23), the second interconnection layer (24), and the insulating film (25), thereby forming a contact hole (27) extending up to the first interconnection layer (22) through these layers (23 and 24), and the insulating film (25). After the formation of the contact hole (27), an aluminum layer (28) is formed on the entire surface of the Insulating film (25) Including the inner surface of the contact hole. The aluminum layer formed on the contact hole electrically interconnects the first and second interconnecting layers (22, 24).

Inventors

  • 👤 Shinji C/O Patent Division Taguchi
  • 👤 Homare C/O Patent Division Matsumura
  • 👤 Kenji C/O Patent Division Maeguchi

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 22:18
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 105 words
A method of manufacturing a semiconductor device characterized by comprising the steps of: forming a first interconnection layer (22, 32) on a semiconductor substrate (21); forming a second interconnection layer (24) on said substrate (21) containing said first interconnection layer (22) with an insulating film (23) interlaying between them; forming a contact hole (27, 34) by etching said insulating film (23) and said second interconnection layer (24) in a step; and forming a conductive layer (28, 35) over the entire upper surface of a semiconductor structure containing said contact hole (27, 34) formed therein, thereby interconnecting said first and second interconnection layers (22, 32; 24).
Claim 2
Independent Claim 105 words
A method of manufacturing a semiconductor device characterized by comprising the steps of: forming a first interconnection layer (22, 32) on a semiconductor substrate (21); forming a second interconnection layer (24) on said substrate (21) containing said first interconnection layer (22) with an insulating film (23) interlaying between them; forming a contact hole (27, 34) by etching said insulating film (23) and said second interconnection layer (24) in a step; and forming a conductive layer (28, 35) over the entire upper surface of a semiconductor structure containing said contact hole (27, 34) formed therein, thereby interconnecting said first and second interconnection layers (22, 32; 24).
Claim 3
Dependent Claim 29 words
The method according to claim 1, characterized in that said first interconnection layer is an impurity diffusion layer (22) formed on the surface region of said semiconductor substrate (21).
Claim 4
Dependent Claim 32 words
The method according to claim 1, characterized in that said first interconnection layer is a conductive layer (32) formed on said semiconductor substrate (21) with an insulating- -layer (31) interlaying between them.
Claim 5
Dependent Claim 17 words
The method according to claim 1, characterized in that said etching process is an anisotropic etching process.
Claim 6
Dependent Claim 26 words
The method according to claim 1, characterized in that said conductive layer (28, 35) is formed while the semiconductor structure is heated at a high temperature.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag