Patent US3293320A successfully refreshed from Google Patents.
EP0127008A2
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EP
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Multi-port register implementations
Assignee: International Business Machines Corp
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Filing: 1984-05-03
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Granted: —
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Expires: 2004-05-03
Abstract
Abstract The present invention is especially directed towards an improved means (24-26) for comparing the address inputs (P1-P3) of word decoders (12-14) in a memory array (10) such that, when a compare occurs, selected ones (13 and/or 14) of the array word decoders are disabled to prevent a multiple read of identical cells (11), and selected higher order read heads (22 and/or 23) are inhibited while switching the output data onto all of the output lines having the same address as the uninhibited word decoder. The comparator circuit (24,25, 26) employs a ripple effect and comprises a plurality of exclusive-OR circuits (69, 69a, 69b) interposed with source follower circuits (72,73). Each of the first and last steps of the comparator is an exclusive-OR circuit. The comparator circuit is extendable to any size system and results in better power performance as well as a smaller size of the array.
Inventors
- 👤 Kerry Bernstein
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 23:55
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/20; G11C8/16
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
218 words
A memory array (10) having bit cells (11) each of which is separately addressable from a plurality of word lines (46, 47, 48) and is readable by a plurality of sets of bit lines (40, 41; 42, 43; 44,45), characterized by: a low order (12; 49) and one or more higher order (13, 14; 50, 51) word decoders coupled to each cell of the array, via said plurality of word lines, a low order (21; 94) and one or more higher order (22, 23; 94a, 94b) read heads coupled to each cell of the array, via said plurality of sets of bit lines, said higher order read heads being equal in number to the number of higher order word decoders, at least one inhibition means (62; 63, 64) coupled to each of said higher order word decoders, at least one multiplexer circuit coupled to each of said higher order read heads, and one or more address comparison means (24; 25, 26) coupled to said inhibition means of said higher order word decoders and said multiplexer circuits of said higher order read heads, for inhibiting a higher order multiple addressing of any cells while switching the read signals due to the uninhibited lower order addressing of said cells to the multiplexer circuits of said higher order read heads involved.
Claim 2
Dependent Claim
218 words
A memory array (10) having bit cells (11) each of which is separately addressable from a plurality of word lines (46, 47, 48) and is readable by a plurality of sets of bit lines (40, 41; 42, 43; 44,45), characterized by: a low order (12; 49) and one or more higher order (13, 14; 50, 51) word decoders coupled to each cell of the array, via said plurality of word lines, a low order (21; 94) and one or more higher order (22, 23; 94a, 94b) read heads coupled to each cell of the array, via said plurality of sets of bit lines, said higher order read heads being equal in number to the number of higher order word decoders, at least one inhibition means (62; 63, 64) coupled to each of said higher order word decoders, at least one multiplexer circuit coupled to each of said higher order read heads, and one or more address comparison means (24; 25, 26) coupled to said inhibition means of said higher order word decoders and said multiplexer circuits of said higher order read heads, for inhibiting a higher order multiple addressing of any cells while switching the read signals due to the uninhibited lower order addressing of said cells to the multiplexer circuits of said higher order read heads involved.
Claim 3
Dependent Claim
121 words
The memory array of claim 1 wherein said address comparison means each comprise: an input stage (69), and a plurality of serially connected compare module circuits (69a, 69b), said input stage being an exclusive-OR circuit (70, 71, 74) coupled to the input of said serially connected compare module circuits, each of said compare module circuits comprising an exclusive-OR circuit (80, 81; 86, 87) coupled to a signal transfer circuit (72; 73), each of said exclusive-OR circuits being coupled to a pair of input address bits which are to be compared, whereby the output of the last of said serially connected compare module circuits provides an address compare signal if and only if each of said pairs of address bits are equal.
Claim 4
Dependent Claim
87 words
The memory array of claim 1 or 2 wherein said address comparison means, in the event of a compare between said addresses, provides a signal to said higher order word decoders to disable selected ones of said higher order word decoders and inhibit selected ones of said higher order read heads from reading more than one set of simultaneously addressed bit lines from the cell while switching the inhibited higher order read heads to output read lines having the same address as the lower order decoder involved.
Claim 5
Dependent Claim
73 words
The memory array of a previous claim wherein each of said sets of bit lines comprises a differential pair of bit lines, each of said read heads comprises a pair of read transistors (90, 91; 98, 99; 102, 103), each of which is coupled to one of said pair of bit lines and to a differential amplifier (94; 94a; 94b), said differential amplifier being coupled to an output read line (96, 96a, 96b).
Claim 6
Dependent Claim
30 words
The memory array of any of claims 1-3 wherein each of said read heads comprises a read transistor coupled to a respective bit line set and to an output amplifier.
Claim 7
Dependent Claim
42 words
The memory array of claim 2 wherein each of said exclusive-OR circuits comprises: a pair of cross coupled field effect transistors (70, 71) having their sources coupled to respective address bits (55, 55a) and their drains coupled to an output line (A).
Claim 8
Dependent Claim
68 words
The memory array of a previous claim wherein said multiplexer circuit comprises: switch means (100, 101) for inhibiting the bit line set (42, 43) coupled to said higher order read head (22), and switch means (97, 90a, 91a) for transferring the input (40, 41) to said lower order read head (21) also to the output amplifier (94a) of the read head (22) to which the multiplexer is coupled.
Claim 9
Dependent Claim
63 words
The memory array of a previous claim wherein said low order (21) and said higher order read heads (22, 23) are arranged serially, said low order read head (21) being the first in said series, each of said higher order read heads (22, 23) being coupled to one multiplexer more than the number of multiplexers to which the preceding read head is coupled.
Claim 10
Dependent Claim
168 words
The memory array of claim 2 or 6 wherein: said input stage (69) comprises an exclusive-OR circuit (70, 71, 74) and being coupled to the input of said serially connected compare modules, each of said compare modules (69a, 69b) comprises an exclusive-OR circuit having a pair of cross-coupled transistors (80, 81; 86, 87) having their inputs coupled to address signal inputs which are to be compared, and each of said compare modules further comprises a source follower stage (72, 73) coupled to the output of a preceding cross-coupled exclusive-OR, said follower stage (72) comprising first and second transistors (76, 77) having their control electrodes coupled to the outputs (A) of said cross-coupled transistors (70, 71) and an inverter transistor (79) having its control electrode coupled to the output of the first inverter transistor (76) and to a voltage source (75) through a load transistor (78) and having its output connected to an output line (B) and to said voltage source (75) through said second source follower transistor (77).
Claim 11
Dependent Claim
107 words
An address comparison circuit (24) characterized by: an input stage (69), and a plurality of serially connected compare module circuits (69a, 69b) coupled to an output line (65), said input stage being an exclusive-OR circuit coupled to the input of said series of module circuits, each of said compare module circuits comprising an exclusive-OR circuit coupled to a signal follower circuit (72, 73), each of said exclusive-OR circuits being coupled to input address bits (55, 55a) and comprising a pair of cross coupled field effect transistors (70, 71) having their sources coupled to respective address bits and their drains coupled to an output line (A, B, 65).
Claim 12
Dependent Claim
107 words
An address comparison circuit (24) characterized by: an input stage (69), and a plurality of serially connected compare module circuits (69a, 69b) coupled to an output line (65), said input stage being an exclusive-OR circuit coupled to the input of said series of module circuits, each of said compare module circuits comprising an exclusive-OR circuit coupled to a signal follower circuit (72, 73), each of said exclusive-OR circuits being coupled to input address bits (55, 55a) and comprising a pair of cross coupled field effect transistors (70, 71) having their sources coupled to respective address bits and their drains coupled to an output line (A, B, 65).
References Cited (Backward Citations)
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