EP0126879A1
Expired / Lapsed
EP
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Integrated circuit arrangement
Assignee: Plessey Overseas Ltd
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Filing: 1984-03-21
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Granted: —
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Expires: 2004-03-21
Abstract
Abstract An integrated circuit arrangement has at least one pair of superposed transistor structures. The arrangement comprises first second and third superposed semiconductor layers (11,12,13) the second layer (12) being of opposite conductivity type to the first (11) and third (13) layers. At least one electrical contact (14) is formed on a surface of the third layer (13) and at least one semiconductive region (16) of the same conductivity type as the second layer (12) is formed in, or on, the said surface of the third layer (13). Electrical connections (17, 21) are made to the or each of the semiconductive regions and the first layer. At least the second and third layers form a heterojunction.
Inventors
- 👤 Geoffrey William Sumerling
- 👤 Robert Charles Goodfellow
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 06:45
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D84/652
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
105 words
An integrated circuit arrangement having at least one pair of superposed transistor structures, the arrangement comprising first, second and third superposed semiconductor layers, the second layer being of opposite conductivity type to the first and third layers, at least one electrical contact formed on a surface of the third layer, at least one semiconductive region of the same conductivity type as the second layer formed in or on the said surface of the third layer, an electrical connection to the or each of the semiconductive region(s) and an electrical connection to the first layer, wherein at least the second and third layers form a heterojunction.
Claim 2
Dependent Claim
105 words
An integrated circuit arrangement having at least one pair of superposed transistor structures, the arrangement comprising first, second and third superposed semiconductor layers, the second layer being of opposite conductivity type to the first and third layers, at least one electrical contact formed on a surface of the third layer, at least one semiconductive region of the same conductivity type as the second layer formed in or on the said surface of the third layer, an electrical connection to the or each of the semiconductive region(s) and an electrical connection to the first layer, wherein at least the second and third layers form a heterojunction.
Claim 3
Dependent Claim
32 words
An integrated circuit arrangement as claimed in claim 1, wherein the electrical contact to the first layer comprises a layer of electrical contact material formed on a surface of the first layer.
Claim 4
Dependent Claim
23 words
An integrated circuit arrangement as claimed in claim 1, wherein the first layer is formed on a semiconductor substrate of like polarity type.
Claim 5
Dependent Claim
20 words
An integrated circuit arrangement as claimed in claim 3, wherein the layers are formed on the substrate by epitaxial deposition.
Claim 6
Dependent Claim
41 words
An integrated circuit arrangement as claimed in claim 3, wherein the substrate is of a conductive type and a layer of contact material is formed on a surface opposite the first layer to provide said electrical connection to the first layer.
Claim 7
Dependent Claim
22 words
An integrated circuit arrangement as claimed in any one of the preceding claims, wherein the first and second layers form a heterojunction.
Claim 8
Dependent Claim
27 words
An integrated circuit arrangement as claimed in any one of the preceding claims, wherein said at least one semiconductive region forms with the third layer a heterojunction.
Claim 9
Dependent Claim
26 words
An integrated circuit arrangement as claimed in any one of the preceding claims, wherein the second layer has a doping density higher than the first layer.
Claim 10
Dependent Claim
34 words
An integrated circuit arrangement as claimed in any one of the preceding claims, wherein the doping density on the wider band gap side of any heterojunction is reduced in the vicinity of that heterojunction.
Claim 11
Dependent Claim
41 words
An integrated circuit arrangement as claimed in any one of the preceding claims, wherein the doping density at the surface of the third layer beneath said at least one electrical contact is more heavily doped than the remainder of the layer.
Claim 12
Dependent Claim
42 words
An integrated circuit arrangement as claimed in any one of claims 1 to 8, wherein the surface of the third layer beneath said at least one electrical contact is arranged to have a wider band gap than the remainder of the layer.
Claim 13
Dependent Claim
43 words
An integrated circuit structure as claimed in any one of the preceding claims provided with N said semiconductive regions forming the collectors of the multicollector I 2 L circuit and wherein the current gain of the transistor is arranged to be substantially 2N.
Claim 14
Dependent Claim
28 words
An integrated circuit structure as claimed in claim 12 where the current gain is limited to 2N by ensuring a sufficient minority carrier recombination at the base contact.
Claim 15
Dependent Claim
21 words
An integrated circuit arrangement as claimed in any one of the preceding claims fabricated in Gallium Arsenide and Gallium Aluminium Arsenide.
Claim 16
Dependent Claim
22 words
An integrated circuit arrangement as claimed in any one of claims 1 to 13 fabricated in Gallium Indium Arsenide and Indium Phosphide.
Claim 17
Dependent Claim
39 words
An integrated circuit arrangement as claimed in any one of claims 1 to 15, wherein the doping density of the third layer is such that said at least one electrical contact forms a Schottky diode with the third layer.
Claim 18
Dependent Claim
40 words
An integrated circuit arrangement as claimed in any one of the preceding claims wherein the first and third layers are of p type conductivity and the second layer and said at least one semiconductive regions are of n type conductivity.
Claim 19
Dependent Claim
105 words
An integrated circuit arrangement as claimed in any one of the preceding claims having a plurality of pairs of superposed transistor structures wherein, the first and second layers are common to all of the pairs and wherein the third layer is divided into a number of separate sections which are isolated from each other and which are each associated with a separate one of the pairs, each of the separate sections having at least one electrical contact formed on the surface thereof, at least one said semiconductive region formed in or on the surface thereof and an electrical contact for each of the semiconductive regions.
Claim 20
Dependent Claim
36 words
An integrated circuit arrangement as claimed in claim 18, wherein the separate sections are isolated frar. each other by an interconnected isolation strip which is adapted to provide an electrical contact rail for the second layer.
Claim 21
Dependent Claim
65 words
An integrated circuit arrangement as claimed in claim 3, or any one of the preceding claims when dependent from claim 3, in which at least one island is formed by providing an isolating region which extends down to the substrate, which island is used to fabricate an individual transistor, diode, resistor, capacitor or circuit on the same chip as the pairs(s) of superposed transistor structures.
Claim 22
Dependent Claim
18 words
An integrated circuit arrangement as claimed in claim 20 wherein the isolating region is formed by mesa etching.
Claim 23
Dependent Claim
18 words
An integrated circuit arrangement as claimed in claim 20 wherein the isolating region is formed by proton implantation.
Claim 24
Dependent Claim
19 words
An integrated circuit arrangement as claimed in claim 20 wherein the isolating region is formed by p-type dopant implantation.
Claim 25
Dependent Claim
13 words
An integrated circuit arrangement substantially as herein described with reference to the drawings.
Claim 26
Dependent Claim
13 words
An integrated circuit arrangement substantially as herein described with reference to the drawings.
References Cited (Backward Citations)
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