EP0126484A2
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EP
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Time switch in a time division switching network
Assignee: Hitachi Ltd
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Filing: 1984-05-22
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Granted: —
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Expires: 2004-05-22
Abstract
Abstract A time switch for a time division switch has a function to exchange time slots as well as functions of bit rate conversion and multiplexing or demultiplexing. A first stage time switch comprises a channel memory (112) capable of sequential writing and random reading and a converter (113) for converting a data read from the channel memory to a universal signal in accordance with a conversion mode designation. A final stage time switch comprises a channel memory (312) capable of random writing and sequential reading and a control circuit (313) for designating a write bit position of the channel memory in accordance with a write mode designation. An economic time switch having a high flexibility to a traffic variation among bearer signals is provided.
Inventors
- 👤 Tetsuo Takemura
- 👤 Shinobu Gohara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 10:00
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/50; H04L12/52; H04L12/525; H04Q; H04Q11/00; H04Q11/04; H04Q11/06
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
102 words
A time switch comprising: a channel memory (112) for writing a data from an incoming highway (201) by a fixed address designation corresponding to a time slot of the incoming highway and reading out the data by a variable address designation corresponding to a time slot of an outgoing highway (208); a converter (113) for converting the data read from said channel memory to a universal signal in accordance with a conversion mode designation; and a control memory (116) for supplying the variable address designation for said channel memory and the conversion mode designation for said converter is synchronism to each other.
Claim 2
Dependent Claim
102 words
A time switch comprising: a channel memory (112) for writing a data from an incoming highway (201) by a fixed address designation corresponding to a time slot of the incoming highway and reading out the data by a variable address designation corresponding to a time slot of an outgoing highway (208); a converter (113) for converting the data read from said channel memory to a universal signal in accordance with a conversion mode designation; and a control memory (116) for supplying the variable address designation for said channel memory and the conversion mode designation for said converter is synchronism to each other.
Claim 3
Dependent Claim
26 words
A time switch according to Claim 1 wherein the conversion mode designation for said converter includes a bit rate class and a conversion bit position designation.
Claim 4
Dependent Claim
49 words
A time switch according to Claim 2 wherein the number of bits of each of the time slots of the incoming highway and the outgoing highway is 8 and the bit rate class is one of 64 Kb/s, 32 Kb/s, 16 Kb/s and 8 Kb/s or any combination thereof.
Claim 5
Dependent Claim
27 words
A time switch according to Claim 3 wherein when the bit rate class is 64 Kb/s, eight input bits to said converter are outputted as they are.
Claim 6
Dependent Claim
55 words
A time switch according to Claim 3 wherein when the bit rate class is 32 Kb/s, eight input bits to said converter are partitioned to two-bit groups each consisting of four bits and converted each one bit of bit group designated by the conversion bit position designation to two bits to produce eight output bits.
Claim 7
Dependent Claim
56 words
A time switch according to Claim 3 wherein when the bit rate class is 16 Kb/s, eight input bits to said converter are partitioned to four-bit groups each consit- ing of two bits and converted each one bit of bit group designated by the conversion bit position designation to four bits to produce eight output bits.
Claim 8
Dependent Claim
48 words
A time switch according to Claim 3 wherein when the bit rate class is 8 Kb/s, eight input bits to said converter are converted to bits consisting of a specified one of the eight bits in accordance with the conversion bit position designation to produce eight output bits.
Claim 9
Dependent Claim
108 words
A time switch comprising: a channel memory (312) for writing a data from an in-highway (410) in accordance with a variable address designation corresponding to a time slot of the incoming highway at only a bit position synchronously designated and reading out the data in accordance with a fixed address designation corresponding to a time slot of an outgoing highway (408); a write control circuit (313) for designating a write bit position of said channel memory in accordance with a write mode designation, and a control memory (316) for supplying the variable address designation for said channel memory and the write mode designation for said write control circuit.
Claim 10
Dependent Claim
108 words
A time switch comprising: a channel memory (312) for writing a data from an in-highway (410) in accordance with a variable address designation corresponding to a time slot of the incoming highway at only a bit position synchronously designated and reading out the data in accordance with a fixed address designation corresponding to a time slot of an outgoing highway (408); a write control circuit (313) for designating a write bit position of said channel memory in accordance with a write mode designation, and a control memory (316) for supplying the variable address designation for said channel memory and the write mode designation for said write control circuit.
Claim 11
Dependent Claim
28 words
A time switch according to Claim 8 wherein the write mode designation for said write control circuit includes a bit rate class and a write bit position designation.
Claim 12
Dependent Claim
41 words
A time switch according to Claim 9 wherein the number of bits of each of the time slots is 8 and the bit rate class is one of 64 Kb/s, 32 Kb/s, 16 Kb/s and 8 Kb/s or a combination thereof.
Claim 13
Dependent Claim
27 words
A time switch according to claim 10 wherein when the bit rate class is 64 Kb/s, all of eight input bits to said channel memory are written.
Claim 14
Dependent Claim
30 words
A time switch according to Claim 10 wherein when the bit rate class is 32 Kb/s, only four specified bits of eight input bits to said channel memory are written.
Claim 15
Dependent Claim
30 words
A time switch according to Claim 10 wherein when the bit rate class is 16 Kb/s, only two speicifed bits of eight input bits to said channel memory are written.
Claim 16
Dependent Claim
30 words
A time switch according to Claim 10 wherein when the bit rate class is 8 Kb/s, only one specified - bit-of eight input bits to said channel memory is written.
Claim 17
Dependent Claim
147 words
A time division switch comprising: a plurality of first stage time switches each including a first channel memory (112) and conversion means (113), said first channel memory being sequentially written and randomly read to allow multiple distribution to a plurality of time slots, said first stage time switches converting the multi-distributed signals to universal signals for each time slot by said conversion means; a plurality of final stage time switches each including a second channel memory (312) and write control means (313), said second channel memory being randomly written and sequentially written, said final stage time switches variably controlling writing to said second channel memory bit by bit by said write control means and converting universal signals to bearer multiplex signals; and a space switch for exchanging time slots between outgoing highways of said first stage time switches and incoming highways of said final stage time switches.
Claim 18
Dependent Claim
147 words
A time division switch comprising: a plurality of first stage time switches each including a first channel memory (112) and conversion means (113), said first channel memory being sequentially written and randomly read to allow multiple distribution to a plurality of time slots, said first stage time switches converting the multi-distributed signals to universal signals for each time slot by said conversion means; a plurality of final stage time switches each including a second channel memory (312) and write control means (313), said second channel memory being randomly written and sequentially written, said final stage time switches variably controlling writing to said second channel memory bit by bit by said write control means and converting universal signals to bearer multiplex signals; and a space switch for exchanging time slots between outgoing highways of said first stage time switches and incoming highways of said final stage time switches.
Claim 19
Dependent Claim
117 words
A time division switch according to Claim 15 wherein said first stage time switches each including: the first channel memory (112) for writing a data from an incoming highway (201) by a fixed address designation corresponding to a time slot of the incoming highway and reading out the data by a variable address designation corresponding to a time slot of an outgoing highway (208); the converter (113) for converting the data read from said first channel memory to a universal signal in accordance with a conversion mode designation, and a control memory (116) for supplying the variable address designation for said first channel memory and the conversion mode designation for said converter in synchronism to each other.
Claim 20
Dependent Claim
124 words
A time division switch according to Claim 15 wherein said final stage time switches each including: the second channel memory (312) for writing a data from an incoming highway (401) in accordance with a variable address designation corresponding to a time slot of the incoming highway at only a bit position synchronously designated and reading out the data in accordance with a fixed address designation corresponding to a time slot of an outgoing highway (408); the write control circuit (313) for designating a write bit position of said second channel memory in accordance with a write mode designation; and a control memory (316) for supplying the variable address designation for said second channel memory and the write mode designation for said write control circuit.
References Cited (Backward Citations)
No citation records indexed.
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