EP0126184A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Input protection circuit and bias method for scaled CMOS devices
Assignee: Motorola Solutions Inc
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Filing: 1983-12-16
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Granted: —
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Expires: 2003-12-16
Abstract
Abstract An integrated circuit and method including a protection circuit (70) for an input to a CMOS device formed on a substrate (12) of a given impurity type has a resistive region (20) of an opposite impurity type to the substrate (12) formed therein, the region (20) having input (46) and output (48) connections thereto. A well (22) of the opposite impurity concentration is also formed in the substrate (12), the well (22) being connected to an electrical ground with respect to a first supply voltage lead (54) to the CMOS device. The first supply voltage lead (54) is electrically isolated from the substrate (12). An area (24) of the given impurity type is formed in the well (22), the area (24) and the output (48) connection being electrically common with the CMOS device input. Finally, a second supply voltage lead (60) is electrically connected to the substrate (12) for biasing the substrate to a second supply voltage level exceeding a first supply voltage level.
Inventors
- 👤 Charles S. Meyer
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 12:21
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/611
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
207 words
An input protection circuit (70) for an input to an integrated circuit CMOS device formed on a substrate (12) of a given impurity type comprising: a resistive region (20) of an opposite impurity type to said substrate formed in said substrate, said region having input (46) and output (48) connections thereto; a well (22) of said opposite impurity concentration formed in said substrate and displaced from said resistive region (20), said well (22) being connected to an electrical ground with respect to a first supply voltage lead (54) to said CMOS device, said first supply voltage lead (54) being electrically isolated from said substrate (12) for receiving a first supply voltage level; an area (24) of said given impurity type formed in said well (22), said area (24) and said output (48) connection of said resistive region (20) being electrically common with said CMOS device input; and a second supply voltage lead (60) electrically connected to said substrate (12) for biasing said substrate (12) to a second supply voltage level exceeding said first supply voltage level whereby an input voltage swing in excess of said first supply voltage level may be applied to said input (46) connection to said resistive region (20) to operate said CMOS device.
Claim 2
Dependent Claim
207 words
An input protection circuit (70) for an input to an integrated circuit CMOS device formed on a substrate (12) of a given impurity type comprising: a resistive region (20) of an opposite impurity type to said substrate formed in said substrate, said region having input (46) and output (48) connections thereto; a well (22) of said opposite impurity concentration formed in said substrate and displaced from said resistive region (20), said well (22) being connected to an electrical ground with respect to a first supply voltage lead (54) to said CMOS device, said first supply voltage lead (54) being electrically isolated from said substrate (12) for receiving a first supply voltage level; an area (24) of said given impurity type formed in said well (22), said area (24) and said output (48) connection of said resistive region (20) being electrically common with said CMOS device input; and a second supply voltage lead (60) electrically connected to said substrate (12) for biasing said substrate (12) to a second supply voltage level exceeding said first supply voltage level whereby an input voltage swing in excess of said first supply voltage level may be applied to said input (46) connection to said resistive region (20) to operate said CMOS device.
Claim 3
Dependent Claim
15 words
The input protection circuit of claim 1 wherein said CMOS device comprises an inverter (18).
Claim 4
Dependent Claim
18 words
3_. The input protection circuit of claim 1 wherein said given impurity type is N type semiconductor material.
Claim 5
Dependent Claim
17 words
The input protection circuit of claim 1 wherein said first supply voltage level is substantially 3.3 volts.
Claim 6
Dependent Claim
17 words
The input protection circuit of claim I wherein said second supply voltage level is substantially 5.0 volts.
Claim 7
Dependent Claim
16 words
The input protection circuit of claim 5 wherein said input voltage swing is substantially 5.0 volts.
Claim 8
Dependent Claim
154 words
A bias method for a scaled CMOS device having an input voltage swing in excess of a first supply voltage level electrically isolated from a substrate (12) of a given impurity type including said CMOS device comprising the steps of: firstly forming a resistive region (20) of an opposite impurity type to said substrate (12) in said substrate (12); providing input (46) and output (48) connections to said resistive region; secondly forming a well (22) of said opposite impurity type in said substrate (12) displaced from said resistive region (20); electrically grounding said well (22) with respect to said first supply voltage level; disposing an area (24) of said given impurity type within said well (22); electrically connecting said area (24) and said output (48) connection to an input of said CMOS aevice; and biasing said substrate (12) by application of a second supply voltage level in excess of said first supply voltage level.
Claim 9
Dependent Claim
154 words
A bias method for a scaled CMOS device having an input voltage swing in excess of a first supply voltage level electrically isolated from a substrate (12) of a given impurity type including said CMOS device comprising the steps of: firstly forming a resistive region (20) of an opposite impurity type to said substrate (12) in said substrate (12); providing input (46) and output (48) connections to said resistive region; secondly forming a well (22) of said opposite impurity type in said substrate (12) displaced from said resistive region (20); electrically grounding said well (22) with respect to said first supply voltage level; disposing an area (24) of said given impurity type within said well (22); electrically connecting said area (24) and said output (48) connection to an input of said CMOS aevice; and biasing said substrate (12) by application of a second supply voltage level in excess of said first supply voltage level.
Claim 10
Dependent Claim
20 words
The bias method of claim 7 wherein said step of firstly forming is carried out using P type semiconductor material.
Claim 11
Dependent Claim
29 words
The bias method of claim 7 wherein said step of biasing said substrate (12) is carried out by means of a second supply voltage level of substantially 5.0 volts.
Claim 12
Dependent Claim
29 words
The bias method of claim 7 wherein said step of biasing said substrate (12) is carried out by means of a first supply voltage level of substantially 3.3 volts.
References Cited (Backward Citations)
No citation records indexed.
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