EP0125790B1
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Frequency synthesisers
Assignee: Marconi Instruments Ltd
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Filing: 1984-04-11
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Granted: 1989-06-21
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Expires: 2004-04-11
Abstract
Abstract A frequency synthesiser produces a variable frequency output using a controllable oscillator and a variable frequency divider which form part of a phase locked loop. The integer division ratio of the divider can be altered during a division cycleto simulate a fractional divisor value. The phase noise or jitter which is caused by the step change in divisor value is removed by altering the divisor value in accordance with the terms of a plurality of sequences, each of which sums to zero and which represents successive rows in a Pascal's triangle. A cascaded sequence of accumulators is used to determine the starting instants of each sequence, and the length of each sequence is dependent on the number of delay lines used. Although only four accumulators are illustrated, more can be added to give any desired degree of phase noise cancellation.
Inventors
- 👤 John Norman Wells
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 23:33
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197; H03L7/1974; H03L7/1976
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
163 words
A frequency synthesiser including a variable frequency oscillator (1), the output of which is fed via a frequency divider (5) having a variable integer divisor value to a phase comparator (7), where it is compared with a reference frequency, the phase comparator being arranged to generate a control signal which is dependent on said comparison and which is used to control the frequency of said oscillator; means (10, 11, 14) responsive to a fractional divisor value for periodically altering the divisor value by a predetermined integer amount so that the effective divisor simulates said fractional divisor value; characterised by said means (14, 15, 16, 17) also being arranged to periodically alter the divisor value in accordance with a plurality of predetermined sequences which represent successive rows of Pascal's triangle, the terms of which all sum to zero so as to offset phase difference present at said phase comparator and which stem from the alteration of the divisor value by said predetermined integer amount.
Claim 2
Dependent Claim
163 words
A frequency synthesiser including a variable frequency oscillator (1), the output of which is fed via a frequency divider (5) having a variable integer divisor value to a phase comparator (7), where it is compared with a reference frequency, the phase comparator being arranged to generate a control signal which is dependent on said comparison and which is used to control the frequency of said oscillator; means (10, 11, 14) responsive to a fractional divisor value for periodically altering the divisor value by a predetermined integer amount so that the effective divisor simulates said fractional divisor value; characterised by said means (14, 15, 16, 17) also being arranged to periodically alter the divisor value in accordance with a plurality of predetermined sequences which represent successive rows of Pascal's triangle, the terms of which all sum to zero so as to offset phase difference present at said phase comparator and which stem from the alteration of the divisor value by said predetermined integer amount.
Claim 3
Dependent Claim
33 words
A frequency synthesiser as claimed in claim 1 and wherein said predetermined sequences are combined to form a composite sequence which is stored for subsequent utilisation as required to modify said divisor value.
Claim 4
Dependent Claim
18 words
A frequency synthesiser as claimed in claim 1 or 2 and wherein said predetermined integer amount is unity.
Claim 5
Dependent Claim
184 words
A frequency synthesiser including a variable frequency oscillator (1), the output of which is fed via a frequency divider (5) having a variable integer divisor value to a phase comparator (7), where it is compared with a reference frequency, the phase comparator being arranged to generate a control signal which is dependent on said comparison and which is used to control the frequency of said oscillator, first clocked accumulator means (14) responsive to a fractional divisor value for periodically altering the divisor value by a predetermined integer amount when its contents reaches or exceeds a predetermined value so that the effective divisor simulates said fractional divisor value; characterised by a cascaded plurality of further clocked accumulator means (15, 16, 17) each of which is arranged to periodically alter the divisor value in accordance with respective predetermined sequences, the terms of which all sum to zero so as to offset phase differences at said phase comparator and which stem from the alteration of the divisor value by said predetermined integer amount, each accumulator means being arranged to integrate the contents of the preceding accumulator means.
Claim 6
Dependent Claim
184 words
A frequency synthesiser including a variable frequency oscillator (1), the output of which is fed via a frequency divider (5) having a variable integer divisor value to a phase comparator (7), where it is compared with a reference frequency, the phase comparator being arranged to generate a control signal which is dependent on said comparison and which is used to control the frequency of said oscillator, first clocked accumulator means (14) responsive to a fractional divisor value for periodically altering the divisor value by a predetermined integer amount when its contents reaches or exceeds a predetermined value so that the effective divisor simulates said fractional divisor value; characterised by a cascaded plurality of further clocked accumulator means (15, 16, 17) each of which is arranged to periodically alter the divisor value in accordance with respective predetermined sequences, the terms of which all sum to zero so as to offset phase differences at said phase comparator and which stem from the alteration of the divisor value by said predetermined integer amount, each accumulator means being arranged to integrate the contents of the preceding accumulator means.
Claim 7
Dependent Claim
29 words
A frequency synthesiser as claimed in claim 4 and wherein each accumulator is arranged to initiate a respective predetermined sequence when its contents reaches or exceeds a predetermined value.
Claim 8
Dependent Claim
20 words
A frequency synthesiser as claimed in claim 5 and wherein said predetermined value is the same for all said accumulators.
Claim 9
Dependent Claim
33 words
A frequency synthesiser as claimed in claim 4, 5 and 6 and wherein all accumulators are clocked at the same frequency, which corresponds to the frequency which is applied to said phase comparator.
Claim 10
Dependent Claim
28 words
A frequency synthesiser as claimed in any of claims 4 to 7 and wherein the number of terms in said predetermined sequences increases progressively for successively cascaded accumulators.
Claim 11
Dependent Claim
22 words
A frequency synthesiser as claimed in claim 1 and wherein the number of terms in said predetermined sequences increases progressively by unity.
Claim 12
Dependent Claim
20 words
A frequency synthesiser as claimed in claim 5 or 6 and wherein the sequences represent successive rows in Pascal's triangle.
Claim 13
Dependent Claim
43 words
A frequency synthesiser as claimed in claim 4, 5, 6 or 7 and wherein the occurrence of the terms in the respective predetermined sequences are spaced apart by periods corresponding to a cycle of the clock frequency at which the accumulators are clocked.
References Cited (Backward Citations)
No citation records indexed.
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