EP0125561A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data-processing system having multi-buffer adapter between a system channel and an input/output bus
Assignee: International Business Machines Corp
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Filing: 1984-05-03
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Granted: —
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Expires: 2004-05-03
Abstract
Abstract A data-processing system (10) has a block-multiplexed system channel (30) coupled to a processing engine (20) and a byte-multiplexed bus (50) coupled to multiple I/O devices (40). A multi-buffer adapter (60) transfers data by cycle-steal (direct memory access) operations between the channel (30) and the bus (50). The adapter has multiple buffers (62) switchable to the channel (30) in a burst mode by a channel interface (61) and to the bus (50) in a byte mode by a device-level interface (63).
Inventors
- 👤 Charles Sidney Burns
- 👤 Michael Ray Crabtree
- 👤 Dwight Allen Gourneau
- 👤 Scott Wayne Hinkel
- 👤 George Albert Lerom
- 👤 Michael John Mayfield
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 11:05
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/282; G06F13/10; G06F13/12; G06F13/122
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
190 words
A data-processing system, comprising a processing engine (20), a system channel (30) coupled to said processing engine (20) and adapted to transfer an entire block of data units in a single burst, a plurality of input/output devices (40), a device-level bus (50) coupled to said devices (40) and adapted to transfer interleaved single data units from more than one of said devices (40) at a time and a multi-buffer adapter (60) coupled to said system channel and to said device-level bus, characterized in that said adapter includes a plurality of first-in/first-out buffers (62) each adapted to hold at least one of said blocks of data units, a channel interface (61) responsive to said system channel (30) for selectively coupling said buffers (62) to said system channel (30) long enough to transfer said entire block of data units between said channel (30) and one of said buffers (62), and a device-level bus interface (63) for sequentially coupling each of said buffers (62) to said device-level bus (50) long enough to transfer an individual one of said data units between said device-level bus (50) and a different one of said devices (40).
Claim 2
Dependent Claim
190 words
A data-processing system, comprising a processing engine (20), a system channel (30) coupled to said processing engine (20) and adapted to transfer an entire block of data units in a single burst, a plurality of input/output devices (40), a device-level bus (50) coupled to said devices (40) and adapted to transfer interleaved single data units from more than one of said devices (40) at a time and a multi-buffer adapter (60) coupled to said system channel and to said device-level bus, characterized in that said adapter includes a plurality of first-in/first-out buffers (62) each adapted to hold at least one of said blocks of data units, a channel interface (61) responsive to said system channel (30) for selectively coupling said buffers (62) to said system channel (30) long enough to transfer said entire block of data units between said channel (30) and one of said buffers (62), and a device-level bus interface (63) for sequentially coupling each of said buffers (62) to said device-level bus (50) long enough to transfer an individual one of said data units between said device-level bus (50) and a different one of said devices (40).
Claim 3
Dependent Claim
41 words
The system of claim 1, wherein said multi-buffer adapter further includes an internal bus (64) coupled directly between said channel interface (61) and said device-level interface (63), for immediate transfer of data between said processing engine (20) and said devices (40).
Claim 4
Dependent Claim
27 words
The system of claim 2, wherein each of said buffers (62) includes a set of parameter registers (612, 6231-6236, 633) selectively loadable from said internal bus (64).
Claim 5
Independent Claim
42 words
The system of any preceding claim, wherein said device-level bus interface (63) includes a controller (631) for cyclically allocating a sequential time slot for each of said buffers (62) to transfer one of said data units to/from one of said devices (40).
Claim 6
Independent Claim
69 words
The system of any preceding claim, wherein each of said buffers (62) includes a first-in/first-out memory (621) for transferring data both to and from said channel interface (61) and both to and from said device-level interface (63), and a buffer controller (622) coupled both to said channel interface (61) and to said device-level interface (63) for controlling said memory (621) and for selectively loading said registers (612, 6231-6236, 633).
Claim 7
Dependent Claim
36 words
The system of claim 5, wherein said registers (612, 6231-6236, 633) specify variable parameters for data transfers into and out of said memory (621), said registers being selectively loadable in response to said buffer controller (622).
Claim 8
Dependent Claim
37 words
The system of claim 5 or 6, wherein said memory (621) includes counter means (6212, 6213, 6216) coupled to said buffer controller (622) for indicating when said memory (621) contains a complete block of said data units.
Claim 9
Independent Claim
35 words
The system of claims 3 through 7, wherein one of said registers (612, 6231-6236, 633) is a buffer-select register (612) for selectively coupling only a particular one of said buffers (62) to said channel (30).
Claim 10
Independent Claim
41 words
The system of claims 3 through 8, wherein one of said registers (612, 6231-6236, 633) is a device-level address register (633) having an output coupled to said device-level bus (50) for specifying one of said devices (40) for a data-unit transfer.
Claim 11
Dependent Claim
42 words
The system of claim 9 wherein said device-level interface controller (631) is adapted to allocate a cyclic command time slot and to couple said internal bus (64) and said address register (633) to said device-level bus (50) during said command time slot.
References Cited (Backward Citations)
No citation records indexed.
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