A method of fabricating integrated circuit structures using replica patterning

Claim 1

A method of defining narrow regions in an underlying semiconductor structure for fabricating an integrated circuit structure characterized by comprising: a) depositing a first layer (12) of material having selected etching characteristics on the underlying semiconductor structure; b) depositing a second layer (13) of material having different etching characteristics from the first layer on the first layer (12); c) removing the first layer and second layer (12, 13) from all of the underlying semiconductor structure except for desired regions each having a periphery which includes a narrow region: d) etching the first layer (12) inward only from the periphery to the narrow region to thereby remove all of the first layer except for the narrow region; e) coating all of the underlying semiconductor structure, except where overlaid by the first layer, with a non-conformal material (15); and f) removing the first layer (12) to expose the underlying semiconductor structure except where overlaid by the non-conformal material, to thereby define the narrow region in the underlying semiconductor structure.

Claim 2

A method of defining narrow regions in an underlying semiconductor structure for fabricating an integrated circuit structure characterized by comprising: a) depositing a first layer (12) of material having selected etching characteristics on the underlying semiconductor structure; b) depositing a second layer (13) of material having different etching characteristics from the first layer on the first layer (12); c) removing the first layer and second layer (12, 13) from all of the underlying semiconductor structure except for desired regions each having a periphery which includes a narrow region: d) etching the first layer (12) inward only from the periphery to the narrow region to thereby remove all of the first layer except for the narrow region; e) coating all of the underlying semiconductor structure, except where overlaid by the first layer, with a non-conformal material (15); and f) removing the first layer (12) to expose the underlying semiconductor structure except where overlaid by the non-conformal material, to thereby define the narrow region in the underlying semiconductor structure.

Claim 5

A method as in any one of claims 1 to 3 characterized in that the step c) of removing the first layer and the second layer (12, 13) comprises anisotropically etching the first layer and the second layer (12, 13).

Claim 6

A method as in any one of claims 1 to 4 characterized in that the step d) of etching the first layer (12) inward comprises isotropically etching the first layer.

Claim 7

A method as in any one of claims 1 to 5 characterized in that the step f) of removing the first layer (12) comprises isotropically etching the first layer (12).

Claim 8

A method as in any one of claims 1 to 6 characterized in that the step a) of coating is followed by the step of removing all of the non-conformal material (15) except where overlaid (15a, 15b) by the second layer (13).

Claim 9

A method as in claims 1 to 7 characterized in that said step of coating (e) comprises: depositing a third layer of said non-conformal material across the semiconductor structure; removing portions of the third layer wherever the third layer traverses an underlying region of the semiconductor structure which is nonplanar to thereby create a smoother surface than in the original semiconductor structure; and depositing a fourth layer of said non-conformal material across the upper surface of the third layer.

Claim 12

A method as in any one of claims 1 to 6 characterized by further comprising : after the step d) and before the step c) removing the second layer and introducing selected impurities into the underlying semiconductor structure using the first layer as a mask; and after the step f) introducing other impurities into the underlying semiconductor structure using the non-conformal material as a mask.

Claim 14

A method of fabricating a transistor structure by using the method of claims 1 to 6, said semiconductor structure including a buried layer (51) of first conductivity type (N) overlaid by epitaxial semiconductor material (52) characterized in that: said first and second layers (53, 54) are deposited on the epitaxial material; said step e) comprises forming a layer (65) of third material containing an opposite conductivity type impurity (P); and in that it further comprises: - forming insulating material (70) over all of the third material (65), - depositing fourth material (72) containing first conductivity type impurities (N) over at least the narrow region; and - treating the third and fourth materials (65, 72) to cause some of the first and opposite conductivity type impurity therein to move into the epitaxial semiconductor material (52).

Claim 17

A method as in any one of claims 13 to 15 characterized in that the step of treating comprises heating the third and fourth materials (65, 72).

Claim 18

A method of defining narrow regions in an underlying semiconductor structure for fabricating an integrated circuit structure characterized by comprising: depositing first (17), second (18), third (12) and fourth (13) layers of material in that order, each having selected etching characteristics, on the underlying semiconductor structure; removing the second (18). third (12) and fourth (13) layers from all of the underlying semiconductor structure except for desired regions, each having a periphery which includes a narrow region; etching the third layer (12) inward only from the periphery to the narrow region to thereby remove all of the third layer except for the narrow region; coating all of the first (17) and second (18) layers with a non-conformal material (15) except where the second layer (18) is overlaid by the third layer (12); anisotropically removing the non-conformal material (15) except where overlaid by the fourth layer (13); removing all remaining portions of the third and fourth layers (12, 13) and all of the second layer (18) except where overlaid by the non-conformal material (15); and laterally etching the second layer (18) inward from all portions of the second layer not coated with non-conformal material.

Claim 19

A method of defining narrow regions in an underlying semiconductor structure for fabricating an integrated circuit structure characterized by comprising: depositing first (17), second (18), third (12) and fourth (13) layers of material in that order, each having selected etching characteristics, on the underlying semiconductor structure; removing the second (18). third (12) and fourth (13) layers from all of the underlying semiconductor structure except for desired regions, each having a periphery which includes a narrow region; etching the third layer (12) inward only from the periphery to the narrow region to thereby remove all of the third layer except for the narrow region; coating all of the first (17) and second (18) layers with a non-conformal material (15) except where the second layer (18) is overlaid by the third layer (12); anisotropically removing the non-conformal material (15) except where overlaid by the fourth layer (13); removing all remaining portions of the third and fourth layers (12, 13) and all of the second layer (18) except where overlaid by the non-conformal material (15); and laterally etching the second layer (18) inward from all portions of the second layer not coated with non-conformal material.