Memory access arrangement in a data processing system

Claim 2

A data processing system for use in accessing in each cycle a memory having a plurality of real addresses in a real address space for storing a plurality of sequences of data elements with the data elements of each sequence stored in those of the real addresses which are spaced apart by a real distance predetermined for each sequence, said data processing system comprising: logical address specifying means for specifying a preselected one of logical addresses of a logical address space in each cycle that is associated with a preselected one of the data elements of each sequence; a distance specifying means for specifying a logical distance associated with the real distance of each sequence in each cycle; deciding means responsive to said logical distance for deciding an element number for each sequence; address calculating means responsive to said preselected logical address, said logical distance, and said element number for calculating specific addresses representative of those of said plurality of real addresses which are equal in number to said element number and spaced apart by the real distance associated with said logical distance and which include a preselected real address loaded with said preselected one of the data elements; and means responsive to said specific addresses for accessing said memory to produce those of the data elements of each sequence in each cycle which are equal in number to said element number and include said preselected one of the data elements.

Claim 3

A data processing system as claimed in Claim 1, said memory being divisible into a plurality of consecutively numbered real pages with each real page subdivided into a plurality of memory locations, each of said real addresses consisting of a real page address and a real internal address, the real page addresses being for accessing the respective real pages, the real internal addresses being for accessing the respective memory locations of each real page, said logical address space being divisible into a plurality of logical pages with each logical page subdivided into logical positions equal in number to the memory locations of each real page, each of said logical addresses consisting of a logical page address and a logical internal address, the logical page addresses specifying the respective logical pages, the logical internal addresses specifying the respective logical positions of each logical page, said preselected logical address consisting of a preselected logical page address and a preselected logical internal address, wherein said address calculating means comprises: address translation means for translating said preselected logical page address into translated real page addresses for use in accessing those at least two of said real pages of which is accessible by said preselected real page address and a remaining at least one of which is numbered consecutive to said one of said at least two real pages; address generating means responsive to said preselected logical page address and said preselected logical internal addresses and said logical distance for generating a predetermined number of local logical addresses one of which is common to at least a part of a combination of said preselected logical page address and (Claim 2 continued) said preselected logical internal address and remaining ones of which are spaced apart by integral multiples of said logical distance from the logical position specified by said preselected logical page and said preselected logical internal addresses; address combining means for combining said translated real page addresses with said local logical addresses to produce local real addresses which are equal in number to said predetermined number and which correspond to said local logical addresses, respectively; and selecting means responsive to said local real addresses and said element number for selecting said specific addresses from said local real addresses.

Claim 4

A data processing system as claimed in Claim 2, wherein said address generating means comprises: supplying means responsive to said preselected logical address and said preselected logical internal address for supplying at least a part of said preselected logical address to said combining means as said one local logical address; calculation means responsive to said logical distance for calculating integral multiples of said logical distance which are equal in number to said predetermined number less one; and summing means for summing said integral multiples and said at least a part of the preselected logical address to supply the remaining local logical addresses to said combining means.

Claim 5

A data processing system as claimed in Claim 3, wherein said address generating means further comprises: additional means coupled to said deciding means and responsive to said logical distance for calculating, in each cycle, one of said logical addresses with reference to said element number and said logical distance to put said one logical address into a leading logical address in the following cycle; and means for supplying said logical specifying means with said leading logical address as the preselected logical address in the following cycle.

Claim 6

A data processing system as claimed in any of Glaims 2, to 4 seid logical pages being equal in number to two to the X-th power, each logical page address being of X bits where X is an integer, said X bits being divisible into a higher significant part of M bits and a lower significant part of N bits, said logical pages being divided into logical page blocks which are equal in number to two to the N-th power and each of which consists of the logical pages equal in number to two to the M-th power, wherein said address translation means comprises: translation buffers, two to the N-th power in number, which are assigned to the respective logical page blocks so as to carry out address translation for each of said logical page blocks and each of which stores at least a part of each logical page block assigned thereto; buffer accessing means responsive to the higher and the lower significant parts of said preselected logical page address for accessing the respective translation buffers in accordance with a prescribed rule-determined by the lower significant part of said (Claim 5 continued) preselected logical page address; and means for keeping one of said translated real page addresses for said one of the real pages and the remaining translated real page address for said remaining real page numbered consecutive to said one real page to access said memory by said one and said remaining translated real page addresses.